From: Eddie Hung <eddie@fpgeh.com>
Date: Sat, 23 Nov 2019 00:52:17 +0000 (-0800)
Subject: write_xaiger back to working with whole modules only
X-Git-Tag: working-ls180~881^2^2~152
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=81548d1ef988d10007706c36df5885f8557de74a;p=yosys.git

write_xaiger back to working with whole modules only
---

diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index 5d125b653..de2f7dd73 100644
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -545,15 +545,12 @@ struct XAigerWriter
 			undriven_bits.erase(bit);
 
 		if (!undriven_bits.empty() && !holes_mode) {
-			bool whole_module = module->design->selected_whole_module(module->name);
 			undriven_bits.sort();
 			for (auto bit : undriven_bits) {
-				if (whole_module)
-					log_warning("Treating undriven bit %s.%s like $anyseq.\n", log_id(module), log_signal(bit));
+				log_warning("Treating undriven bit %s.%s like $anyseq.\n", log_id(module), log_signal(bit));
 				input_bits.insert(bit);
 			}
-			if (whole_module)
-				log_warning("Treating a total of %d undriven bits in %s like $anyseq.\n", GetSize(undriven_bits), log_id(module));
+			log_warning("Treating a total of %d undriven bits in %s like $anyseq.\n", GetSize(undriven_bits), log_id(module));
 		}
 
 		if (holes_mode) {