From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 22 Feb 2020 23:36:48 +0000 (+0000)
Subject: append actual bit, see if coriolis issue goes away
X-Git-Tag: ls180-24jan2020~128
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=815a127c73ecb0a92bb521c7b7ceb0c8c1111d88;p=ieee754fpu.git

append actual bit, see if coriolis issue goes away
---

diff --git a/src/ieee754/part_shift/part_shift_dynamic.py b/src/ieee754/part_shift/part_shift_dynamic.py
index daa1ec07..04a6bec0 100644
--- a/src/ieee754/part_shift/part_shift_dynamic.py
+++ b/src/ieee754/part_shift/part_shift_dynamic.py
@@ -37,10 +37,12 @@ class ShifterMask(Elaboratable):
         bits = Signal(self.pwid, reset_less=True)
         bl = []
         for j in range(self.pwid):
+            bit = Signal(self.pwid, name="bit%d" % j, reset_less=True)
             if j != 0:
-                bl.append((~self.gates[j]) & bits[j-1])
+                comb += bit.eq((~self.gates[j]) & bl[j-1])
             else:
-                bl.append(~self.gates[j])
+                comb += bit.eq(~self.gates[j])
+            bl.append(bit)
         # XXX ARGH, really annoying: simulation bug, can't use Cat(*bl).
         for j in range(bits.shape()[0]):
             comb += bits[j].eq(bl[j])