From: whitequark <cz@m-labs.hk>
Date: Sun, 7 Jul 2019 01:03:59 +0000 (+0000)
Subject: hdl.dsl: further clarify error message for incorrect nesting.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=81707a174022aef1700aa371b2ae4ee941db256d;p=nmigen.git

hdl.dsl: further clarify error message for incorrect nesting.

Fixes #133.
---

diff --git a/nmigen/hdl/dsl.py b/nmigen/hdl/dsl.py
index a2cec0b..43da83a 100644
--- a/nmigen/hdl/dsl.py
+++ b/nmigen/hdl/dsl.py
@@ -133,8 +133,14 @@ class Module(_ModuleBuilderRoot, Elaboratable):
                 raise SyntaxError("{} is not permitted outside of {}"
                                   .format(construct, context))
             else:
-                raise SyntaxError("{} is not permitted directly inside of {}"
-                                  .format(construct, self._ctrl_context))
+                if self._ctrl_context == "Switch":
+                    secondary_context = "Case"
+                if self._ctrl_context == "FSM":
+                    secondary_context = "State"
+                raise SyntaxError("{} is not permitted directly inside of {}; it is permitted "
+                                  "inside of {} {}"
+                                  .format(construct, self._ctrl_context,
+                                          self._ctrl_context, secondary_context))
 
     def _get_ctrl(self, name):
         if self._ctrl_stack:
diff --git a/nmigen/test/test_hdl_dsl.py b/nmigen/test/test_hdl_dsl.py
index e01b083..43f83d2 100644
--- a/nmigen/test/test_hdl_dsl.py
+++ b/nmigen/test/test_hdl_dsl.py
@@ -345,7 +345,8 @@ class DSLTestCase(FHDLTestCase):
         m = Module()
         with m.Switch(self.s1):
             with self.assertRaises(SyntaxError,
-                    msg="If is not permitted directly inside of Switch"):
+                    msg="If is not permitted directly inside of Switch; "
+                        "it is permitted inside of Switch Case"):
                 with m.If(self.s2):
                     pass
 
@@ -486,7 +487,8 @@ class DSLTestCase(FHDLTestCase):
             with m.State("FOO"):
                 pass
             with self.assertRaises(SyntaxError,
-                    msg="If is not permitted directly inside of FSM"):
+                    msg="If is not permitted directly inside of FSM; "
+                        "it is permitted inside of FSM State"):
                 with m.If(self.s2):
                     pass