From: Marcelina Kościelnicka <mwk@0x04.net>
Date: Tue, 30 Jun 2020 13:31:12 +0000 (+0200)
Subject: simcells: Fix reset polarity for $_DLATCH_???_ cells.
X-Git-Tag: working-ls180~439
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=817ae04ee0c445efaf83e9847d4956f2dae0d857;p=yosys.git

simcells: Fix reset polarity for $_DLATCH_???_ cells.
---

diff --git a/techlibs/common/gen_fine_ffs.py b/techlibs/common/gen_fine_ffs.py
index e92d58f40..5d331e767 100644
--- a/techlibs/common/gen_fine_ffs.py
+++ b/techlibs/common/gen_fine_ffs.py
@@ -300,7 +300,7 @@ module \$_DLATCH_{E:N|P}{R:N|P}{V:0|1}_ (E, R, D, Q);
 input E, R, D;
 output reg Q;
 always @* begin
-	if (R == {E:0|1})
+	if (R == {R:0|1})
                 Q <= {V:0|1};
 	else if (E == {E:0|1})
 		Q <= D;
diff --git a/techlibs/common/simcells.v b/techlibs/common/simcells.v
index 01b5bdfa6..27ef44232 100644
--- a/techlibs/common/simcells.v
+++ b/techlibs/common/simcells.v
@@ -2986,7 +2986,7 @@ module \$_DLATCH_NP0_ (E, R, D, Q);
 input E, R, D;
 output reg Q;
 always @* begin
-	if (R == 0)
+	if (R == 1)
                 Q <= 0;
 	else if (E == 0)
 		Q <= D;
@@ -3009,7 +3009,7 @@ module \$_DLATCH_NP1_ (E, R, D, Q);
 input E, R, D;
 output reg Q;
 always @* begin
-	if (R == 0)
+	if (R == 1)
                 Q <= 1;
 	else if (E == 0)
 		Q <= D;
@@ -3032,7 +3032,7 @@ module \$_DLATCH_PN0_ (E, R, D, Q);
 input E, R, D;
 output reg Q;
 always @* begin
-	if (R == 1)
+	if (R == 0)
                 Q <= 0;
 	else if (E == 1)
 		Q <= D;
@@ -3055,7 +3055,7 @@ module \$_DLATCH_PN1_ (E, R, D, Q);
 input E, R, D;
 output reg Q;
 always @* begin
-	if (R == 1)
+	if (R == 0)
                 Q <= 1;
 	else if (E == 1)
 		Q <= D;