From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 27 Oct 2019 09:25:01 +0000 (+0100)
Subject: Merge pull request #1393 from whitequark/write_verilog-avoid-init
X-Git-Tag: working-ls180~974
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=81876a3734dacde199446343ce338b24e9b2796f;p=yosys.git

Merge pull request #1393 from whitequark/write_verilog-avoid-init

write_verilog: do not print (*init*) attributes on regs
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81876a3734dacde199446343ce338b24e9b2796f