From: Gabe Black Date: Wed, 29 Mar 2006 00:36:34 +0000 (-0500) Subject: SPARC compiles for SE! X-Git-Tag: m5_2.0_beta1~149^2 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=818f3ae22f324601742801b166350691cddf3a2a;p=gem5.git SPARC compiles for SE! arch/sparc/isa/decoder.isa: Replaced register number munging with RdLow and RdHigh operands. arch/sparc/isa/formats/mem.isa: Fixed how the address calculation code is dealt with. arch/sparc/isa/operands.isa: Changed the tabbing so that the whole oeprands block was consistent, and added RdLow and RdHigh operands. These registers are used when Rd is meant to refer to a pair of registers, rather than just one. arch/sparc/isa_traits.hh: Moved some functions to the new (to SPARC) utility.hh file. Also, dummy Fpcr_DepTag and Uniq_DepTag DepTags were added to pacify Tru64. These need to be removed, and Tru64 needs to not be compiled in if it isn't appropriate. arch/sparc/regfile.hh: Changed regSpace to have the correct size. arch/sparc/utility.hh: A new file for sparc to match the one for alpha. --HG-- extra : convert_revision : ff6b529093d15f327ec11f067ad533bacdba9932 --- diff --git a/arch/sparc/isa/decoder.isa b/arch/sparc/isa/decoder.isa index ca8d22419..6c1356932 100644 --- a/arch/sparc/isa/decoder.isa +++ b/arch/sparc/isa/decoder.isa @@ -444,14 +444,14 @@ decode OP default Unknown::unknown() 0x02: lduh({{Rd.uhw = Mem.uhw;}}); //LDUH 0x03: ldd({{ uint64_t val = Mem.udw; - setIntReg(RD & (~1), val<31:0>); - setIntReg(RD | 1, val<63:32>); + RdLow = val<31:0>; + RdHigh = val<63:32>; }});//LDD 0x04: stw({{Mem.sw = Rd.sw;}}); //STW 0x05: stb({{Mem.sb = Rd.sb;}}); //STB 0x06: sth({{Mem.shw = Rd.shw;}}); //STH 0x07: std({{ - Mem.udw = readIntReg(RD & (~1))<31:0> | (readIntReg(RD | 1)<31:0> << 32); + Mem.udw = RdLow<31:0> | RdHigh<31:0> << 32; }});//STD 0x08: ldsw({{Rd.sw = Mem.sw;}}); //LDSW 0x09: ldsb({{Rd.sb = Mem.sb;}}); //LDSB @@ -473,14 +473,14 @@ decode OP default Unknown::unknown() 0x12: lduha({{Rd.uhw = Mem.uhw;}}); //LDUHA 0x13: ldda({{ uint64_t val = Mem.udw; - setIntReg(RD & (~1), val<31:0>); - setIntReg(RD | 1, val<63:32>); + RdLow = val<31:0>; + RdHigh = val<63:32>; }}); //LDDA 0x14: stwa({{Mem.uw = Rd.uw;}}); //STWA 0x15: stba({{Mem.ub = Rd.ub;}}); //STBA 0x16: stha({{Mem.uhw = Rd.uhw;}}); //STHA 0x17: stda({{ - Mem.udw = readIntReg(RD & (~1))<31:0> | (readIntReg(RD | 1)<31:0> << 32); + Mem.udw = RdLow<31:0> | RdHigh<31:0> << 32; }}); //STDA 0x18: ldswa({{Rd.sw = Mem.sw;}}); //LDSWA 0x19: ldsba({{Rd.sb = Mem.sb;}}); //LDSBA diff --git a/arch/sparc/isa/formats/mem.isa b/arch/sparc/isa/formats/mem.isa index cf6e7d95b..f1162e24b 100644 --- a/arch/sparc/isa/formats/mem.isa +++ b/arch/sparc/isa/formats/mem.isa @@ -52,10 +52,15 @@ def template MemExecute {{ // Primary format for integer operate instructions: def format Mem(code, *opt_flags) {{ - orig_code = code - cblk = CodeBlock(code) - iop = InstObjParams(name, Name, 'SparcStaticInst', cblk, opt_flags) - iop.ea_code = CodeBlock('EA = I ? (R1 + SIMM13) : R1 + R2;').code + addrCalc = 'EA = I ? (Rs1 + SIMM13) : Rs1 + Rs2;' + composite = code + '\n' + addrCalc + origCodeBlk = CodeBlock(code) + compositeBlk = CodeBlock(composite) + addrCalcBlk = CodeBlock(addrCalc) + iop = InstObjParams(name, Name, 'SparcStaticInst', compositeBlk, opt_flags) + iop.code = origCodeBlk.code + iop.orig_code = origCodeBlk.orig_code + iop.ea_code = addrCalcBlk.code header_output = BasicDeclare.subst(iop) decoder_output = BasicConstructor.subst(iop) decode_block = BasicDecode.subst(iop) diff --git a/arch/sparc/isa/operands.isa b/arch/sparc/isa/operands.isa index abfdf7bcd..0d521fae0 100644 --- a/arch/sparc/isa/operands.isa +++ b/arch/sparc/isa/operands.isa @@ -16,18 +16,20 @@ def operands {{ # Int regs default to unsigned, but code should not count on this. # For clarity, descriptions that depend on unsigned behavior should # explicitly specify '.uq'. - 'Rd': ('IntReg', 'udw', 'RD', 'IsInteger', 1), - 'Rs1': ('IntReg', 'udw', 'RS1', 'IsInteger', 2), - 'Rs2': ('IntReg', 'udw', 'RS2', 'IsInteger', 3), + 'Rd': ('IntReg', 'udw', 'RD', 'IsInteger', 1), + 'RdLow': ('IntReg', 'udw', 'RD & (~1)', 'IsInteger', 2), + 'RdHigh': ('IntReg', 'udw', 'RD | 1', 'IsInteger', 3), + 'Rs1': ('IntReg', 'udw', 'RS1', 'IsInteger', 4), + 'Rs2': ('IntReg', 'udw', 'RS2', 'IsInteger', 5), #'Fa': ('FloatReg', 'df', 'FA', 'IsFloating', 1), #'Fb': ('FloatReg', 'df', 'FB', 'IsFloating', 2), #'Fc': ('FloatReg', 'df', 'FC', 'IsFloating', 3), - 'Mem': ('Mem', 'udw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4), + 'Mem': ('Mem', 'udw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4), #'NPC': ('NPC', 'uq', None, ( None, None, 'IsControl' ), 4), #'Runiq': ('ControlReg', 'uq', 'Uniq', None, 1), #'FPCR': ('ControlReg', 'uq', 'Fpcr', None, 1), - 'R0': ('IntReg', 'udw', '0', None, 1), - 'R16': ('IntReg', 'udw', '16', None, 1), + 'R0': ('IntReg', 'udw', '0', None, 1), + 'R16': ('IntReg', 'udw', '16', None, 1), # Control registers 'Pstate': ('ControlReg', 'udw', 'MISCREG_PSTATE', None, 1), 'PstateAg': ('ControlReg', 'udw', 'MISCREG_PSTATE_AG', None, 2), diff --git a/arch/sparc/isa_traits.hh b/arch/sparc/isa_traits.hh index 4886da7cf..6cf77eb0e 100644 --- a/arch/sparc/isa_traits.hh +++ b/arch/sparc/isa_traits.hh @@ -90,6 +90,9 @@ namespace SparcISA // 32..63 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag) FP_Base_DepTag = 32, Ctrl_Base_DepTag = 96, + //XXX These are here solely to get compilation and won't work + Fpcr_DepTag = 0, + Uniq_DepTag = 0 }; //This makes sure the big endian versions of certain functions are used. @@ -98,11 +101,6 @@ namespace SparcISA typedef uint32_t MachInst; typedef uint64_t ExtMachInst; - inline ExtMachInst - makeExtMI(MachInst inst, const Addr &pc) { - return ExtMachInst(inst); - } - const int NumIntRegs = 32; const int NumFloatRegs = 64; const int NumMiscRegs = 32; @@ -160,31 +158,6 @@ namespace SparcISA // return a no-op instruction... used for instruction fetch faults extern const MachInst NoopMachInst; - - // Instruction address compression hooks - inline Addr realPCToFetchPC(const Addr &addr) - { - return addr; - } - - inline Addr fetchPCToRealPC(const Addr &addr) - { - return addr; - } - - // the size of "fetched" instructions (not necessarily the size - // of real instructions for PISA) - inline size_t fetchInstSize() - { - return sizeof(MachInst); - } - - /** - * Function to insure ISA semantics about 0 registers. - * @param xc The execution context. - */ - template - void zeroRegisters(XC *xc); } #include "arch/sparc/regfile.hh" diff --git a/arch/sparc/regfile.hh b/arch/sparc/regfile.hh index 944fdfe80..09b8e49d7 100644 --- a/arch/sparc/regfile.hh +++ b/arch/sparc/regfile.hh @@ -55,15 +55,15 @@ namespace SparcISA class FloatRegFile { protected: - //Since the floating point registers overlap each other, - //A generic storage space is used. The float to be returned is - //pulled from the appropriate section of this region. - char regSpace[32 * 64]; - static const int SingleWidth = 32; static const int DoubleWidth = 64; static const int QuadWidth = 128; + //Since the floating point registers overlap each other, + //A generic storage space is used. The float to be returned is + //pulled from the appropriate section of this region. + char regSpace[SingleWidth / 8 * NumFloatRegs]; + public: FloatReg readReg(int floatReg, int width) diff --git a/arch/sparc/utility.hh b/arch/sparc/utility.hh new file mode 100644 index 000000000..1e67b3370 --- /dev/null +++ b/arch/sparc/utility.hh @@ -0,0 +1,89 @@ +/* + * Copyright (c) 2003-2005 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __ARCH_SPARC_UTILITY_HH__ +#define __ARCH_SPARC_UTILITY_HH__ + +#include "arch/sparc/isa_traits.hh" +#include "base/misc.hh" + +namespace SparcISA +{ + inline ExtMachInst + makeExtMI(MachInst inst, const Addr &pc) { + return ExtMachInst(inst); + } + + inline bool isCallerSaveIntegerRegister(unsigned int reg) { + panic("register classification not implemented"); + return false; + } + + inline bool isCalleeSaveIntegerRegister(unsigned int reg) { + panic("register classification not implemented"); + return false; + } + + inline bool isCallerSaveFloatRegister(unsigned int reg) { + panic("register classification not implemented"); + return false; + } + + inline bool isCalleeSaveFloatRegister(unsigned int reg) { + panic("register classification not implemented"); + return false; + } + + // Instruction address compression hooks + inline Addr realPCToFetchPC(const Addr &addr) + { + return addr; + } + + inline Addr fetchPCToRealPC(const Addr &addr) + { + return addr; + } + + // the size of "fetched" instructions (not necessarily the size + // of real instructions for PISA) + inline size_t fetchInstSize() + { + return sizeof(MachInst); + } + + /** + * Function to insure ISA semantics about 0 registers. + * @param xc The execution context. + */ + template + void zeroRegisters(XC *xc); + +} // namespace SparcISA + +#endif