From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 11 Feb 2022 13:57:18 +0000 (+0000)
Subject: add ulx3s option to Makefile, fix "no uart_top"
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=818f8182ba03fd929d548d42fe2ac80ea29bcc82;p=microwatt.git

add ulx3s option to Makefile, fix "no uart_top"
---

diff --git a/Makefile b/Makefile
index 678bbfa..672a84a 100644
--- a/Makefile
+++ b/Makefile
@@ -158,6 +158,19 @@ OPENOCD_JTAG_CONFIG=openocd/olimex-arm-usb-tiny-h.cfg
 OPENOCD_DEVICE_CONFIG=openocd/LFE5UM5G-85F.cfg
 endif
 
+# ULX3S with ECP85
+ifeq ($(FPGA_TARGET), ULX3S)
+RESET_LOW=true
+CLK_INPUT=25000000
+CLK_FREQUENCY=25000000
+LPF=constraints/ulx3s.lpf
+PACKAGE=CABGA381
+NEXTPNR_FLAGS=--um5g-85k --freq 25
+OPENOCD_JTAG_CONFIG=openocd/ulx3s.cfg
+OPENOCD_DEVICE_CONFIG=openocd/LFE5UM5G-85F.cfg
+endif
+
+
 # ECP5-EVN
 ifeq ($(FPGA_TARGET), ECP5-EVN)
 RESET_LOW=true
@@ -191,7 +204,8 @@ fpga_files = $(core_files) $(soc_files) fpga/soc_reset.vhdl \
 synth_files = $(core_files) $(soc_files) $(fpga_files) $(clkgen) $(toplevel) $(dmi_dtm)
 
 microwatt.json: $(synth_files) $(RAM_INIT_FILE)
-	$(YOSYS) -m $(GHDLSYNTH) -p "ghdl --std=08 --no-formal $(GHDL_IMAGE_GENERICS) $(GHDL_TARGET_GENERICS) $(synth_files) -e toplevel; synth_ecp5 -json $@  $(SYNTH_ECP5_FLAGS)" $(uart_files)
+	$(YOSYS) -m $(GHDLSYNTH) -p "ghdl --std=08 --no-formal $(GHDL_IMAGE_GENERICS) $(GHDL_TARGET_GENERICS) $(synth_files) -e toplevel; read_verilog $(uart_files) $(soc_extra_v); synth_ecp5 -abc9 -nowidelut -json $@  $(SYNTH_ECP5_FLAGS)"
+
 
 microwatt.v: $(synth_files) $(RAM_INIT_FILE)
 	$(YOSYS) -m $(GHDLSYNTH) -p "ghdl --std=08 --no-formal $(GHDL_IMAGE_GENERICS) $(GHDL_TARGET_GENERICS) $(synth_files) -e toplevel; write_verilog $@"
diff --git a/constraints/ulx3s.lpf b/constraints/ulx3s.lpf
new file mode 100644
index 0000000..234c341
--- /dev/null
+++ b/constraints/ulx3s.lpf
@@ -0,0 +1,20 @@
+LOCATE COMP "ext_clk" SITE "G2";
+IOBUF PORT "ext_clk" IO_TYPE=LVCMOS33 PULLMODE=NONE;
+FREQUENCY PORT "ext_clk" 25 MHZ;
+
+LOCATE COMP "ext_rst" SITE "D6";
+IOBUF PORT "ext_rst" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+
+LOCATE COMP "uart0_txd" SITE "L4";
+LOCATE COMP "uart0_rxd" SITE "M1";
+
+IOBUF PORT "uart0_txd" IO_TYPE=LVCMOS33 PULLMODE=UP DRIVE=4;
+IOBUF PORT "uart0_rxd" IO_TYPE=LVCMOS33 PULLMODE=UP;
+
+LOCATE COMP "led_a" SITE "B2";
+LOCATE COMP "led_b" SITE "C2";
+LOCATE COMP "led_c" SITE "C1";
+
+IOBUF PORT "led_a" IO_TYPE=LVCMOS25 DRIVE=4 PULLMODE=NONE;
+IOBUF PORT "led_b" IO_TYPE=LVCMOS25 DRIVE=4 PULLMODE=NONE;
+IOBUF PORT "led_c" IO_TYPE=LVCMOS25 DRIVE=4 PULLMODE=NONE;
diff --git a/openocd/ulx3s.cfg b/openocd/ulx3s.cfg
new file mode 100644
index 0000000..b4adbba
--- /dev/null
+++ b/openocd/ulx3s.cfg
@@ -0,0 +1,11 @@
+interface ft232r
+ft232r_vid_pid 0x0403 0x6015
+# ULX3S specific GPIO setting
+ft232r_tck_num DSR
+ft232r_tms_num DCD
+ft232r_tdi_num RI
+ft232r_tdo_num CTS
+# trst/srst are not used but must have different values than above
+ft232r_trst_num RTS
+ft232r_srst_num DTR
+adapter_khz 1000