From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 2 Jul 2019 15:22:31 +0000 (-0700)
Subject: Update test for Pass::call_on_module()
X-Git-Tag: working-ls180~1227^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=81a717e9b767792f64535757f905a5061c627fbd;p=yosys.git

Update test for Pass::call_on_module()
---

diff --git a/tests/various/script.ys b/tests/various/script.ys
index 4152145e8..66b7b5caa 100644
--- a/tests/various/script.ys
+++ b/tests/various/script.ys
@@ -9,7 +9,7 @@ read_verilog -formal <<EOT
     endmodule
 
     module other;
-        wire [1023:0] _DELETE = "delete c:bar";
+        wire [1023:0] _DELETE = "cd; delete c:bar";
     endmodule
 EOT