From: Luke Kenneth Casson Leighton Date: Wed, 17 Nov 2021 17:42:05 +0000 (+0000) Subject: core hazard bitvector regfiles need to be readable X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=81b013cceefaec4457df0e75a1aab8ab8fb3c30f;p=soc.git core hazard bitvector regfiles need to be readable immediately (combinatorial) not via sync. allow synced option to pass through from VirtualRegPort to RegFileArray --- diff --git a/src/soc/regfile/regfiles.py b/src/soc/regfile/regfiles.py index fc87bee9..234c06e7 100644 --- a/src/soc/regfile/regfiles.py +++ b/src/soc/regfile/regfiles.py @@ -285,9 +285,9 @@ class RegFiles: def make_hazard_vec(self, rf, name): if isinstance(rf, VirtualRegPort): - vec = VirtualRegPort(rf.nregs, rf.nregs, wr2=True) + vec = VirtualRegPort(rf.nregs, rf.nregs, wr2=True, synced=False) else: - vec = VirtualRegPort(rf.depth, rf.depth, wr2=True) + vec = VirtualRegPort(rf.depth, rf.depth, wr2=True, synced=False) # get read/write port specs and create bitvector ports with same names wr_spec, rd_spec = rf.get_port_specs() # ok, this is complicated/fun. diff --git a/src/soc/regfile/virtual_port.py b/src/soc/regfile/virtual_port.py index dc5c57d6..78a61240 100644 --- a/src/soc/regfile/virtual_port.py +++ b/src/soc/regfile/virtual_port.py @@ -18,13 +18,13 @@ from soc.regfile.regfile import RegFileArray class VirtualRegPort(RegFileArray): - def __init__(self, bitwidth, n_regs, rd2=False, wr2=False): + def __init__(self, bitwidth, n_regs, rd2=False, wr2=False, synced=True): self.bitwidth = bitwidth self.nregs = n_regs self.rd2 = rd2 # eurgh hack self.wr2 = wr2 # eurgh hack self.regwidth = regwidth = bitwidth // n_regs - super().__init__(self.regwidth, n_regs) + super().__init__(self.regwidth, n_regs, synced=synced) # "full" depth variant of the "external" port self.full_wr = RecordObject([("wen", n_regs),