From: Segher Boessenkool <segher@kernel.crashing.org>
Date: Mon, 30 Jul 2018 16:11:44 +0000 (+0200)
Subject: testcase for 2-2 combine
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=81bdfc1e2940fc93bcd0bba4416daff47f04f3b3;p=gcc.git

testcase for 2-2 combine


gcc/testsuite/
	PR rtl-optimization/85160
	* gcc.target/powerpc/combine-2-2.c: New testcase.

From-SVN: r263072
---

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 3850aaa0ebd..0731143de66 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2018-07-30  Segher Boessenkool  <segher@kernel.crashing.org>
+
+	PR rtl-optimization/85160
+	* gcc.target/powerpc/combine-2-2.c: New testcase.
+
 2018-07-27  Martin Sebor  <msebor@redhat.com>
 
 	PR tree-optimization/86696
diff --git a/gcc/testsuite/gcc.target/powerpc/combine-2-2.c b/gcc/testsuite/gcc.target/powerpc/combine-2-2.c
new file mode 100644
index 00000000000..234476d5b5e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/combine-2-2.c
@@ -0,0 +1,17 @@
+/* { dg-options "-O2" } */
+
+/* PR85160 */
+
+/* Originally, the "x >> 14" are CSEd away (eventually becoming a srawi
+   instruction), and the two ANDs remain separate instructions because
+   combine cannot deal with this.
+
+   Now that combine knows how to combine two RTL insns into two, it manages
+   to make this just the sum of two rlwinm instructions.  */
+
+int f(int x)
+{
+  return ((x >> 14) & 6) + ((x >> 14) & 4);
+}
+
+/* { dg-final { scan-assembler-not {\msrawi\M} } } */