From: Eric Engestrom Date: Thu, 16 Aug 2018 14:41:53 +0000 (+0100) Subject: intel: various python cleanups X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=81c1989e4ff229d6fc49fab1c01eaab3d81432dc;p=mesa.git intel: various python cleanups Signed-off-by: Eric Engestrom Reviewed-by: Emil Velikov --- diff --git a/src/intel/genxml/gen_bits_header.py b/src/intel/genxml/gen_bits_header.py index dcd6ccb7d9e..ded2d2dcfcf 100644 --- a/src/intel/genxml/gen_bits_header.py +++ b/src/intel/genxml/gen_bits_header.py @@ -25,7 +25,6 @@ from __future__ import ( import argparse import os -import sys import xml.parsers.expat from mako.template import Template diff --git a/src/intel/genxml/gen_pack_header.py b/src/intel/genxml/gen_pack_header.py index c3d712c7a86..0bf838de8c6 100644 --- a/src/intel/genxml/gen_pack_header.py +++ b/src/intel/genxml/gen_pack_header.py @@ -219,9 +219,9 @@ def safe_name(name): def num_from_str(num_str): if num_str.lower().startswith('0x'): return int(num_str, base=16) - else: - assert not num_str.startswith('0'), 'octals numbers not allowed' - return int(num_str) + + assert not num_str.startswith('0'), 'octals numbers not allowed' + return int(num_str) class Field(object): ufixed_pattern = re.compile(r"u(\d+)\.(\d+)") @@ -306,7 +306,7 @@ class Field(object): print(" %-36s %s%s;" % (type, self.name, dim)) prefix = "" - if len(self.values) > 0 and self.default == None: + if self.values and self.default == None: if self.prefix: prefix = self.prefix + "_" @@ -340,7 +340,7 @@ class Group(object): def collect_dwords(self, dwords, start, dim): for field in self.fields: - if type(field) is Group: + if isinstance(field, Group): if field.count == 1: field.collect_dwords(dwords, start + field.start, dim) else: @@ -424,7 +424,7 @@ class Group(object): # to the dword for those fields. field_index = 0 for field in dw.fields: - if type(field) is Field and field.is_struct_type(): + if isinstance(field, Field) and field.is_struct_type(): name = field.name + field.dim print("") print(" uint32_t v%d_%d;" % (index, field_index)) @@ -490,7 +490,7 @@ class Group(object): non_address_fields.append("/* unhandled field %s, type %s */\n" % \ (name, field.type)) - if len(non_address_fields) > 0: + if non_address_fields: print(" |\n".join(" " + f for f in non_address_fields) + ";") if dw.size == 32: @@ -531,8 +531,7 @@ class Parser(object): def gen_prefix(self, name): if name[0] == "_": return 'GEN%s%s' % (self.gen, name) - else: - return 'GEN%s_%s' % (self.gen, name) + return 'GEN%s_%s' % (self.gen, name) def gen_guard(self): return self.gen_prefix("PACK_H") @@ -629,7 +628,7 @@ class Parser(object): def emit_instruction(self): name = self.instruction - if not self.length == None: + if not self.length is None: print('#define %-33s %6d' % (self.gen_prefix(name + "_length"), self.length)) print('#define %-33s %6d' % @@ -637,9 +636,9 @@ class Parser(object): default_fields = [] for field in self.group.fields: - if not type(field) is Field: + if not isinstance(field, Field): continue - if field.default == None: + if field.default is None: continue default_fields.append(" .%-35s = %6d" % (field.name, field.default)) @@ -654,11 +653,11 @@ class Parser(object): def emit_register(self): name = self.register - if not self.reg_num == None: + if not self.reg_num is None: print('#define %-33s 0x%04x' % (self.gen_prefix(name + "_num"), self.reg_num)) - if not self.length == None: + if not self.length is None: print('#define %-33s %6d' % (self.gen_prefix(name + "_length"), self.length)) @@ -667,7 +666,7 @@ class Parser(object): def emit_struct(self): name = self.struct - if not self.length == None: + if not self.length is None: print('#define %-33s %6d' % (self.gen_prefix(name + "_length"), self.length)) diff --git a/src/intel/genxml/gen_zipped_file.py b/src/intel/genxml/gen_zipped_file.py index 616409183f0..199f550419e 100644 --- a/src/intel/genxml/gen_zipped_file.py +++ b/src/intel/genxml/gen_zipped_file.py @@ -23,7 +23,6 @@ # from __future__ import print_function -import os import sys import zlib import xml.etree.cElementTree as et diff --git a/src/intel/isl/gen_format_layout.py b/src/intel/isl/gen_format_layout.py index 1fa7c6267df..c1f22707fb9 100644 --- a/src/intel/isl/gen_format_layout.py +++ b/src/intel/isl/gen_format_layout.py @@ -25,7 +25,6 @@ from __future__ import absolute_import, division, print_function import argparse import csv import re -import textwrap from mako import template @@ -150,7 +149,7 @@ class Channel(object): self.size = int(grouped.group('size')) # Default the start bit to -1 - self.start = -1; + self.start = -1 class Format(object): @@ -177,7 +176,7 @@ class Format(object): bit = 0 for c in self.order: chan = getattr(self, c) - chan.start = bit; + chan.start = bit bit = bit + chan.size # alpha doesn't have a colorspace of it's own. @@ -217,13 +216,13 @@ def get_srgb_to_linear_map(formats): ('U8SRGB', 'FLT16'), ] - found = False; + found = False for rep in replacements: rgb_name = fmt.name.replace(rep[0], rep[1]) if rgb_name in names: found = True yield fmt.name, rgb_name - break; + break # We should have found a format name assert found diff --git a/src/intel/vulkan/anv_extensions.py b/src/intel/vulkan/anv_extensions.py index 9a65aed1c46..cafb6060c6b 100644 --- a/src/intel/vulkan/anv_extensions.py +++ b/src/intel/vulkan/anv_extensions.py @@ -32,10 +32,9 @@ import xml.etree.cElementTree as et def _bool_to_c_expr(b): if b is True: return 'true' - elif b is False: + if b is False: return 'false' - else: - return b + return b class Extension: def __init__(self, name, ext_version, enable): @@ -142,7 +141,7 @@ class VkVersion: # VK_MAKE_VERSION macro assert self.major < 1024 and self.minor < 1024 assert self.patch is None or self.patch < 4096 - assert(str(self) == string) + assert str(self) == string def __str__(self): ver_list = [str(self.major), str(self.minor)]