From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 19 Mar 2020 23:59:11 +0000 (-0700)
Subject: opt_expr: add $xor/$xnor/$_XOR_/$_XNOR_ tests
X-Git-Tag: working-ls180~708^2~4
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=81ca776ea44e126b3946fcdd076c2d2e4d2ab34d;p=yosys.git

opt_expr: add $xor/$xnor/$_XOR_/$_XNOR_ tests
---

diff --git a/tests/opt/opt_expr_xor.ys b/tests/opt/opt_expr_xor.ys
new file mode 100644
index 000000000..a458c9a27
--- /dev/null
+++ b/tests/opt/opt_expr_xor.ys
@@ -0,0 +1,40 @@
+read_verilog <<EOT
+module top(input a, output [3:0] y);
+assign y[0] = a^1'b0;
+assign y[1] = 1'b1^a;
+assign y[2] = a~^1'b0;
+assign y[3] = 1'b1^~a;
+endmodule
+EOT
+design -save read
+select -assert-count 2 t:$xor
+select -assert-count 2 t:$xnor
+
+equiv_opt opt_expr
+design -load postopt
+select -assert-none t:$xor
+select -assert-none t:$xnor
+select -assert-count 2 t:$_NOT_
+
+
+design -load read
+simplemap
+equiv_opt opt_expr
+design -load postopt
+select -assert-none t:$_XOR_
+select -assert-none t:$_XNOR_ # NB: simplemap does $xnor -> $_XOR_+$_NOT_
+select -assert-count 3 t:$_NOT_
+
+
+design -reset
+read_verilog -icells <<EOT
+module top(input a, output [1:0] y);
+$_XNOR_ u0(.A(a), .B(1'b0), .Y(y[0]));
+$_XNOR_ u1(.A(1'b1), .B(a), .Y(y[1]));
+endmodule
+EOT
+select -assert-count 2 t:$_XNOR_
+equiv_opt opt_expr
+design -load postopt
+select -assert-none t:$_XNOR_ # NB: simplemap does $xnor -> $_XOR_+$_NOT_
+select -assert-count 1 t:$_NOT_