From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 10 Nov 2021 19:07:46 +0000 (+0000)
Subject: display 64 bits of msr
X-Git-Tag: sv_maxu_works-initial~758
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=81ef8d694c5d5b5f58c962916fdbc28f162e893b;p=openpower-isa.git

display 64 bits of msr
---

diff --git a/src/openpower/test/runner.py b/src/openpower/test/runner.py
index c429ee14..f7ce2186 100644
--- a/src/openpower/test/runner.py
+++ b/src/openpower/test/runner.py
@@ -381,7 +381,7 @@ class TestRunnerBase(FHDLTestCase):
 
         traces += [('ld/st port interface', {'submodule': pi_module}, [
             'oper_r__insn_type',
-            'oper_r__msr',
+            'oper_r__msr[63:0]',
             'ldst_port0_is_ld_i',
             'ldst_port0_is_st_i',
             'ldst_port0_busy_o',