From: lkcl <lkcl@web>
Date: Wed, 3 Mar 2021 13:10:27 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~98
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=82074f46e780fd0a0374d41192275050f455268d;p=libreriscv.git

---

diff --git a/openpower/sv/implementation.mdwn b/openpower/sv/implementation.mdwn
index 28adf0f8d..ed356000a 100644
--- a/openpower/sv/implementation.mdwn
+++ b/openpower/sv/implementation.mdwn
@@ -104,6 +104,14 @@ Progress:
 
 * <https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/sv/svstate.py;hb=HEAD>
 
+## Adding SVSTATE "set/get" support for hw/sw debugging
+
+This includes adding DMI get/set support in hardware as well as gdb (remote) support.
+
+* LibreSOC DMI/JTAG: TODO
+* Microwatt DMI: TODO
+* power-gem5 remote gdb: TODO 
+
 ## sv.setvl
 
 a [[sv/setvl]] instruction is needed, which also implements [[sv/sprs]] i.e. primarily the `SVSTATE` SPR.  the dual-access SPRs for VL and MVL which mirror into the SVSTATE.VL and SVSTATE.MVL fields are not immediately essential to implement.