From: lkcl <lkcl@web>
Date: Wed, 4 Aug 2021 12:26:59 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~508
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=820f9cddc1fc57115832e7cfa7a7b2277425bea0;p=libreriscv.git

---

diff --git a/openpower/sv/branches.mdwn b/openpower/sv/branches.mdwn
index aeb7b7718..82de8682d 100644
--- a/openpower/sv/branches.mdwn
+++ b/openpower/sv/branches.mdwn
@@ -149,6 +149,20 @@ Available options to combine:
 * `ALL` or `ANY` behaviour corresponding to `AND` of all tests and
   `OR` of all tests, respectively.
 
+Pseudocode for Rc in sv.bc
+
+```
+# Use bit 30, disable AA
+Rc = AA
+AA = 0
+```
+
+Pseudocode for Rc in sv.bclr
+
+```
+Rc = instr[16]
+```
+
 Pseudocode for Horizontal-First Mode:
 
 ```