From: Sebastien Bourdeauducq <sb@m-labs.hk>
Date: Tue, 22 Sep 2015 16:36:47 +0000 (+0800)
Subject: migen.fhdl.std -> migen
X-Git-Tag: 24jan2021_ls180~2106^2~52
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=82236d9b40d4066df4adabfc119832cdc5aaa7b6;p=litex.git

migen.fhdl.std -> migen
---

diff --git a/misoc/com/gpio.py b/misoc/com/gpio.py
index 88a49040..6db225fb 100644
--- a/misoc/com/gpio.py
+++ b/misoc/com/gpio.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.genlib.cdc import MultiReg
 from migen.bank.description import *
 
diff --git a/misoc/com/liteethmini/common.py b/misoc/com/liteethmini/common.py
index a5f0b3fc..21d0da08 100644
--- a/misoc/com/liteethmini/common.py
+++ b/misoc/com/liteethmini/common.py
@@ -1,7 +1,7 @@
 import math
 from collections import OrderedDict
 
-from migen.fhdl.std import *
+from migen import *
 from migen.genlib.resetsync import AsyncResetSynchronizer
 from migen.genlib.record import *
 from migen.genlib.fsm import FSM, NextState
diff --git a/misoc/com/spi/__init__.py b/misoc/com/spi/__init__.py
index a78a6db4..029a0bec 100644
--- a/misoc/com/spi/__init__.py
+++ b/misoc/com/spi/__init__.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.bank.description import *
 from migen.genlib.fsm import FSM, NextState
 
diff --git a/misoc/com/spi/test/spi_master_tb.py b/misoc/com/spi/test/spi_master_tb.py
index 51a30c66..e0febf53 100644
--- a/misoc/com/spi/test/spi_master_tb.py
+++ b/misoc/com/spi/test/spi_master_tb.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.genlib.record import *
 from migen.sim.generic import run_simulation
 
diff --git a/misoc/com/uart/__init__.py b/misoc/com/uart/__init__.py
index ffc39b48..bc00e506 100644
--- a/misoc/com/uart/__init__.py
+++ b/misoc/com/uart/__init__.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.bank.description import *
 from migen.bank.eventmanager import *
 from migen.genlib.record import Record
diff --git a/misoc/com/uart/bridge.py b/misoc/com/uart/bridge.py
index 6917f355..61cc098b 100644
--- a/misoc/com/uart/bridge.py
+++ b/misoc/com/uart/bridge.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 
 from misoc.tools.wishbone import WishboneStreamingBridge
 from misoc.com.uart.phy.serial import UARTPHYSerial
diff --git a/misoc/com/uart/phy/serial.py b/misoc/com/uart/phy/serial.py
index 747dbd21..6458d4e3 100644
--- a/misoc/com/uart/phy/serial.py
+++ b/misoc/com/uart/phy/serial.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.genlib.cdc import MultiReg
 from migen.bank.description import *
 from migen.flow.actor import Sink, Source
diff --git a/misoc/com/uart/phy/sim.py b/misoc/com/uart/phy/sim.py
index a7348e0b..85a215d5 100644
--- a/misoc/com/uart/phy/sim.py
+++ b/misoc/com/uart/phy/sim.py
@@ -2,7 +2,7 @@ import os
 import pty
 import time
 
-from migen.fhdl.std import *
+from migen import *
 from migen.flow.actor import Sink, Source
 
 
diff --git a/misoc/cpu/identifier.py b/misoc/cpu/identifier.py
index 7f24c612..a70f44b0 100644
--- a/misoc/cpu/identifier.py
+++ b/misoc/cpu/identifier.py
@@ -1,6 +1,6 @@
 import subprocess
 
-from migen.fhdl.std import *
+from migen import *
 from migen.bank.description import *
 
 def get_id():
diff --git a/misoc/cpu/lm32.py b/misoc/cpu/lm32.py
index 8ea7637b..ca9b001c 100644
--- a/misoc/cpu/lm32.py
+++ b/misoc/cpu/lm32.py
@@ -1,6 +1,6 @@
 import os
 
-from migen.fhdl.std import *
+from migen import *
 from migen.bus import wishbone
 
 
diff --git a/misoc/cpu/mor1kx.py b/misoc/cpu/mor1kx.py
index 1169aba7..f9c69642 100644
--- a/misoc/cpu/mor1kx.py
+++ b/misoc/cpu/mor1kx.py
@@ -1,6 +1,6 @@
 import os
 
-from migen.fhdl.std import *
+from migen import *
 from migen.bus import wishbone
 
 
diff --git a/misoc/cpu/timer.py b/misoc/cpu/timer.py
index 4061f837..62a88acf 100644
--- a/misoc/cpu/timer.py
+++ b/misoc/cpu/timer.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.bank.description import *
 from migen.bank.eventmanager import *
 
diff --git a/misoc/mem/flash/norflash16.py b/misoc/mem/flash/norflash16.py
index 42c68c07..2649a4ae 100644
--- a/misoc/mem/flash/norflash16.py
+++ b/misoc/mem/flash/norflash16.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.bus import wishbone
 from migen.genlib.fsm import FSM, NextState
 
diff --git a/misoc/mem/flash/spiflash.py b/misoc/mem/flash/spiflash.py
index 1e099a75..b63840c5 100644
--- a/misoc/mem/flash/spiflash.py
+++ b/misoc/mem/flash/spiflash.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.bus.transactions import *
 from migen.bus import wishbone
 from migen.genlib.misc import timeline
diff --git a/misoc/mem/sdram/core/__init__.py b/misoc/mem/sdram/core/__init__.py
index 287bdf57..6d7057f1 100644
--- a/misoc/mem/sdram/core/__init__.py
+++ b/misoc/mem/sdram/core/__init__.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.genlib.record import *
 from migen.bank.description import *
 
diff --git a/misoc/mem/sdram/core/lasmibus.py b/misoc/mem/sdram/core/lasmibus.py
index c1d3b0cd..acdb3702 100644
--- a/misoc/mem/sdram/core/lasmibus.py
+++ b/misoc/mem/sdram/core/lasmibus.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.bus.transactions import *
 from migen.genlib import roundrobin
 from migen.genlib.record import *
diff --git a/misoc/mem/sdram/core/lasmicon/__init__.py b/misoc/mem/sdram/core/lasmicon/__init__.py
index 170e085a..e06a167d 100644
--- a/misoc/mem/sdram/core/lasmicon/__init__.py
+++ b/misoc/mem/sdram/core/lasmicon/__init__.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 
 from misoc.mem.sdram.phy import dfi
 from misoc.mem.sdram.core import lasmibus
diff --git a/misoc/mem/sdram/core/lasmicon/bankmachine.py b/misoc/mem/sdram/core/lasmicon/bankmachine.py
index 1f58dd43..4e3cbd65 100644
--- a/misoc/mem/sdram/core/lasmicon/bankmachine.py
+++ b/misoc/mem/sdram/core/lasmicon/bankmachine.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.genlib.roundrobin import *
 from migen.genlib.fsm import FSM, NextState
 from migen.genlib.misc import optree
diff --git a/misoc/mem/sdram/core/lasmicon/multiplexer.py b/misoc/mem/sdram/core/lasmicon/multiplexer.py
index d03d4dfd..150fe1cc 100644
--- a/misoc/mem/sdram/core/lasmicon/multiplexer.py
+++ b/misoc/mem/sdram/core/lasmicon/multiplexer.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.genlib.roundrobin import *
 from migen.genlib.misc import optree
 from migen.genlib.fsm import FSM, NextState
diff --git a/misoc/mem/sdram/core/lasmicon/perf.py b/misoc/mem/sdram/core/lasmicon/perf.py
index 2c7e8cf0..2283adc0 100644
--- a/misoc/mem/sdram/core/lasmicon/perf.py
+++ b/misoc/mem/sdram/core/lasmicon/perf.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.bank.description import *
 
 
diff --git a/misoc/mem/sdram/core/lasmicon/refresher.py b/misoc/mem/sdram/core/lasmicon/refresher.py
index 12aeefc4..8af685fc 100644
--- a/misoc/mem/sdram/core/lasmicon/refresher.py
+++ b/misoc/mem/sdram/core/lasmicon/refresher.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.genlib.misc import timeline
 from migen.genlib.fsm import FSM
 
diff --git a/misoc/mem/sdram/core/lasmixbar.py b/misoc/mem/sdram/core/lasmixbar.py
index cbba9499..1af682ec 100644
--- a/misoc/mem/sdram/core/lasmixbar.py
+++ b/misoc/mem/sdram/core/lasmixbar.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.genlib import roundrobin
 from migen.genlib.record import *
 from migen.genlib.misc import optree
diff --git a/misoc/mem/sdram/core/minicon/__init__.py b/misoc/mem/sdram/core/minicon/__init__.py
index dd70f58c..dcb48e5d 100644
--- a/misoc/mem/sdram/core/minicon/__init__.py
+++ b/misoc/mem/sdram/core/minicon/__init__.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.bus import wishbone
 from migen.genlib.fsm import FSM, NextState
 from migen.genlib.misc import optree, WaitTimer
diff --git a/misoc/mem/sdram/frontend/dma_lasmi.py b/misoc/mem/sdram/frontend/dma_lasmi.py
index 54c48433..b505b3ed 100644
--- a/misoc/mem/sdram/frontend/dma_lasmi.py
+++ b/misoc/mem/sdram/frontend/dma_lasmi.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.flow.actor import *
 from migen.genlib.fifo import SyncFIFO
 
diff --git a/misoc/mem/sdram/frontend/memtest.py b/misoc/mem/sdram/frontend/memtest.py
index 9b3c62a3..58d56233 100644
--- a/misoc/mem/sdram/frontend/memtest.py
+++ b/misoc/mem/sdram/frontend/memtest.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.genlib.misc import optree
 from migen.bank.description import *
 from migen.actorlib.spi import *
diff --git a/misoc/mem/sdram/frontend/wishbone2lasmi.py b/misoc/mem/sdram/frontend/wishbone2lasmi.py
index 9524734a..d1dfd1bc 100644
--- a/misoc/mem/sdram/frontend/wishbone2lasmi.py
+++ b/misoc/mem/sdram/frontend/wishbone2lasmi.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.genlib.fsm import FSM, NextState
 
 class WB2LASMI(Module):
diff --git a/misoc/mem/sdram/module.py b/misoc/mem/sdram/module.py
index f15867d8..bf1ce74f 100644
--- a/misoc/mem/sdram/module.py
+++ b/misoc/mem/sdram/module.py
@@ -16,7 +16,7 @@
 
 from math import ceil
 
-from migen.fhdl.std import *
+from migen import *
 from misoc.mem import sdram
 
 
diff --git a/misoc/mem/sdram/phy/dfi.py b/misoc/mem/sdram/phy/dfi.py
index 76379e28..aae56b0d 100644
--- a/misoc/mem/sdram/phy/dfi.py
+++ b/misoc/mem/sdram/phy/dfi.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.genlib.record import *
 
 
diff --git a/misoc/mem/sdram/phy/dfii.py b/misoc/mem/sdram/phy/dfii.py
index ffbdc7dd..b79b8d94 100644
--- a/misoc/mem/sdram/phy/dfii.py
+++ b/misoc/mem/sdram/phy/dfii.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.bank.description import *
 
 from misoc.mem.sdram.phy import dfi
diff --git a/misoc/mem/sdram/phy/gensdrphy.py b/misoc/mem/sdram/phy/gensdrphy.py
index 80c589d6..a349cdf5 100644
--- a/misoc/mem/sdram/phy/gensdrphy.py
+++ b/misoc/mem/sdram/phy/gensdrphy.py
@@ -21,7 +21,7 @@
 # This PHY only supports CAS Latency 2.
 #
 
-from migen.fhdl.std import *
+from migen import *
 from migen.genlib.record import *
 from migen.fhdl.specials import *
 
diff --git a/misoc/mem/sdram/phy/initsequence.py b/misoc/mem/sdram/phy/initsequence.py
index 3bdf5f3a..8ca1db00 100644
--- a/misoc/mem/sdram/phy/initsequence.py
+++ b/misoc/mem/sdram/phy/initsequence.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import log2_int
+from migen import log2_int
 
 
 def get_sdram_phy_header(sdram_phy_settings):
diff --git a/misoc/mem/sdram/phy/k7ddrphy.py b/misoc/mem/sdram/phy/k7ddrphy.py
index 5a2e0fc9..044a7123 100644
--- a/misoc/mem/sdram/phy/k7ddrphy.py
+++ b/misoc/mem/sdram/phy/k7ddrphy.py
@@ -1,6 +1,6 @@
 # tCK=5ns CL=7 CWL=6
 
-from migen.fhdl.std import *
+from migen import *
 from migen.bank.description import *
 
 from misoc.mem.sdram.phy.dfi import *
diff --git a/misoc/mem/sdram/phy/s6ddrphy.py b/misoc/mem/sdram/phy/s6ddrphy.py
index 7153f05c..c2f7e12e 100644
--- a/misoc/mem/sdram/phy/s6ddrphy.py
+++ b/misoc/mem/sdram/phy/s6ddrphy.py
@@ -16,7 +16,7 @@
 # Write commands must be sent on phase 1.
 #
 
-from migen.fhdl.std import *
+from migen import *
 from migen.genlib.record import *
 
 from misoc.mem.sdram.phy.dfi import *
diff --git a/misoc/mem/sdram/phy/simphy.py b/misoc/mem/sdram/phy/simphy.py
index 0588d082..6b8bcf19 100644
--- a/misoc/mem/sdram/phy/simphy.py
+++ b/misoc/mem/sdram/phy/simphy.py
@@ -6,7 +6,7 @@
 # TODO:
 # - add $display support to Migen and manage timing violations?
 
-from migen.fhdl.std import *
+from migen import *
 from migen.fhdl.specials import *
 from misoc.mem.sdram.phy.dfi import *
 from misoc.mem import sdram
diff --git a/misoc/mem/sdram/test/abstract_transactions_lasmi.py b/misoc/mem/sdram/test/abstract_transactions_lasmi.py
index fd027f75..18d77963 100644
--- a/misoc/mem/sdram/test/abstract_transactions_lasmi.py
+++ b/misoc/mem/sdram/test/abstract_transactions_lasmi.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.bus.transactions import *
 from migen.sim.generic import run_simulation
 
diff --git a/misoc/mem/sdram/test/bankmachine_tb.py b/misoc/mem/sdram/test/bankmachine_tb.py
index 54578dce..020d1268 100644
--- a/misoc/mem/sdram/test/bankmachine_tb.py
+++ b/misoc/mem/sdram/test/bankmachine_tb.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.sim.generic import run_simulation
 
 from misoc.mem.sdram.code import lasmibus
diff --git a/misoc/mem/sdram/test/common.py b/misoc/mem/sdram/test/common.py
index 6c1c09dd..8a537484 100644
--- a/misoc/mem/sdram/test/common.py
+++ b/misoc/mem/sdram/test/common.py
@@ -1,7 +1,7 @@
 from fractions import Fraction
 from math import ceil
 
-from migen.fhdl.std import *
+from migen import *
 
 from misoc import sdram
 
diff --git a/misoc/mem/sdram/test/lasmicon_df_tb.py b/misoc/mem/sdram/test/lasmicon_df_tb.py
index bee4a7d4..326d56a1 100644
--- a/misoc/mem/sdram/test/lasmicon_df_tb.py
+++ b/misoc/mem/sdram/test/lasmicon_df_tb.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.sim.generic import run_simulation
 
 from misoc.mem.sdram.core import lasmibus
diff --git a/misoc/mem/sdram/test/lasmicon_tb.py b/misoc/mem/sdram/test/lasmicon_tb.py
index 957e3e71..469f8eb8 100644
--- a/misoc/mem/sdram/test/lasmicon_tb.py
+++ b/misoc/mem/sdram/test/lasmicon_tb.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.sim.generic import run_simulation
 
 from misoc.mem.sdram.core import lasmibus
diff --git a/misoc/mem/sdram/test/lasmicon_wb.py b/misoc/mem/sdram/test/lasmicon_wb.py
index 425bdf71..37c5b031 100644
--- a/misoc/mem/sdram/test/lasmicon_wb.py
+++ b/misoc/mem/sdram/test/lasmicon_wb.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.bus import wishbone
 from migen.bus.transactions import *
 from migen.sim.generic import run_simulation
diff --git a/misoc/mem/sdram/test/minicon_tb.py b/misoc/mem/sdram/test/minicon_tb.py
index 8aa4f899..8468d5f2 100644
--- a/misoc/mem/sdram/test/minicon_tb.py
+++ b/misoc/mem/sdram/test/minicon_tb.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.bus.transactions import TRead, TWrite
 from migen.bus import wishbone
 from migen.sim.generic import Simulator
diff --git a/misoc/mem/sdram/test/refresher.py b/misoc/mem/sdram/test/refresher.py
index 4a13c19e..5722b09d 100644
--- a/misoc/mem/sdram/test/refresher.py
+++ b/misoc/mem/sdram/test/refresher.py
@@ -1,6 +1,6 @@
 from random import Random
 
-from migen.fhdl.std import *
+from migen import *
 from migen.sim.generic import run_simulation
 
 from misoc.mem.sdram.core.lasmicon.refresher import *
diff --git a/misoc/soc/__init__.py b/misoc/soc/__init__.py
index 889be51d..c114dbb1 100644
--- a/misoc/soc/__init__.py
+++ b/misoc/soc/__init__.py
@@ -1,6 +1,6 @@
 from operator import itemgetter
 
-from migen.fhdl.std import *
+from migen import *
 from migen.bank import csrgen
 from migen.bus import wishbone, csr, wishbone2csr
 
diff --git a/misoc/soc/cpuif.py b/misoc/soc/cpuif.py
index ac812d51..3ed2dd6d 100644
--- a/misoc/soc/cpuif.py
+++ b/misoc/soc/cpuif.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.bank.description import CSRStatus
 
 
diff --git a/misoc/soc/sdram.py b/misoc/soc/sdram.py
index d46beb1c..e8d86a70 100644
--- a/misoc/soc/sdram.py
+++ b/misoc/soc/sdram.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.bus import wishbone
 from migen.genlib.record import *
 
diff --git a/misoc/tools/wishbone.py b/misoc/tools/wishbone.py
index 5b712bf8..99b4c43e 100644
--- a/misoc/tools/wishbone.py
+++ b/misoc/tools/wishbone.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.bus import wishbone
 from migen.genlib.misc import chooser, Counter, WaitTimer
 from migen.genlib.record import Record
diff --git a/misoc/video/dvisampler/__init__.py b/misoc/video/dvisampler/__init__.py
index 1670ccfa..fad0f9da 100644
--- a/misoc/video/dvisampler/__init__.py
+++ b/misoc/video/dvisampler/__init__.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.bank.description import AutoCSR
 
 from misoc.video.dvisampler.edid import EDID
diff --git a/misoc/video/dvisampler/analysis.py b/misoc/video/dvisampler/analysis.py
index 77003c72..189413fe 100644
--- a/misoc/video/dvisampler/analysis.py
+++ b/misoc/video/dvisampler/analysis.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.genlib.cdc import MultiReg, PulseSynchronizer
 from migen.genlib.fifo import AsyncFIFO
 from migen.genlib.record import Record
diff --git a/misoc/video/dvisampler/chansync.py b/misoc/video/dvisampler/chansync.py
index b83b8188..3bd3fdba 100644
--- a/misoc/video/dvisampler/chansync.py
+++ b/misoc/video/dvisampler/chansync.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.genlib.cdc import MultiReg
 from migen.genlib.fifo import _inc
 from migen.genlib.record import Record, layout_len
diff --git a/misoc/video/dvisampler/charsync.py b/misoc/video/dvisampler/charsync.py
index 102da27d..93b0e556 100644
--- a/misoc/video/dvisampler/charsync.py
+++ b/misoc/video/dvisampler/charsync.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.genlib.cdc import MultiReg
 from migen.genlib.misc import optree
 from migen.bank.description import *
diff --git a/misoc/video/dvisampler/clocking.py b/misoc/video/dvisampler/clocking.py
index d13b1fb9..0fc8969b 100644
--- a/misoc/video/dvisampler/clocking.py
+++ b/misoc/video/dvisampler/clocking.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.genlib.cdc import MultiReg
 from migen.bank.description import *
 
diff --git a/misoc/video/dvisampler/datacapture.py b/misoc/video/dvisampler/datacapture.py
index 8e91ad04..49f0ccef 100644
--- a/misoc/video/dvisampler/datacapture.py
+++ b/misoc/video/dvisampler/datacapture.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.genlib.cdc import MultiReg, PulseSynchronizer
 from migen.bank.description import *
 
diff --git a/misoc/video/dvisampler/debug.py b/misoc/video/dvisampler/debug.py
index 67af06e6..9e561383 100644
--- a/misoc/video/dvisampler/debug.py
+++ b/misoc/video/dvisampler/debug.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.genlib.fifo import AsyncFIFO
 from migen.genlib.record import layout_len
 from migen.bank.description import AutoCSR
diff --git a/misoc/video/dvisampler/decoding.py b/misoc/video/dvisampler/decoding.py
index 2d0ddbf4..fd8c0c61 100644
--- a/misoc/video/dvisampler/decoding.py
+++ b/misoc/video/dvisampler/decoding.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.genlib.record import Record
 
 from misoc.video.dvisampler.common import control_tokens, channel_layout
diff --git a/misoc/video/dvisampler/dma.py b/misoc/video/dvisampler/dma.py
index 75458df7..7ed4f829 100644
--- a/misoc/video/dvisampler/dma.py
+++ b/misoc/video/dvisampler/dma.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.genlib.fsm import FSM, NextState
 from migen.bank.description import *
 from migen.bank.eventmanager import *
diff --git a/misoc/video/dvisampler/edid.py b/misoc/video/dvisampler/edid.py
index 2a8e8b08..eb674b3e 100644
--- a/misoc/video/dvisampler/edid.py
+++ b/misoc/video/dvisampler/edid.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.fhdl.specials import Tristate
 from migen.genlib.cdc import MultiReg
 from migen.genlib.fsm import FSM, NextState
diff --git a/misoc/video/dvisampler/wer.py b/misoc/video/dvisampler/wer.py
index 310e6d48..39d20289 100644
--- a/misoc/video/dvisampler/wer.py
+++ b/misoc/video/dvisampler/wer.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.bank.description import *
 from migen.genlib.misc import optree
 from migen.genlib.cdc import PulseSynchronizer
diff --git a/misoc/video/framebuffer/__init__.py b/misoc/video/framebuffer/__init__.py
index eec9404b..5071c943 100644
--- a/misoc/video/framebuffer/__init__.py
+++ b/misoc/video/framebuffer/__init__.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.flow.network import *
 from migen.flow import plumbing
 from migen.bank.description import AutoCSR
diff --git a/misoc/video/framebuffer/dvi.py b/misoc/video/framebuffer/dvi.py
index 0ba8b4b4..03bb6acd 100644
--- a/misoc/video/framebuffer/dvi.py
+++ b/misoc/video/framebuffer/dvi.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.genlib.misc import optree
 
 control_tokens = [0b1101010100, 0b0010101011, 0b0101010100, 0b1010101011]
diff --git a/misoc/video/framebuffer/format.py b/misoc/video/framebuffer/format.py
index e3a3931f..210ec5ce 100644
--- a/misoc/video/framebuffer/format.py
+++ b/misoc/video/framebuffer/format.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.flow.actor import *
 from migen.bank.description import CSRStorage
 from migen.genlib.record import Record
diff --git a/misoc/video/framebuffer/phy.py b/misoc/video/framebuffer/phy.py
index d77426c5..2bb128fb 100644
--- a/misoc/video/framebuffer/phy.py
+++ b/misoc/video/framebuffer/phy.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.genlib.fifo import AsyncFIFO
 from migen.genlib.cdc import MultiReg
 from migen.bank.description import *
diff --git a/targets/de0nano.py b/targets/de0nano.py
index d823b0a6..46641236 100644
--- a/targets/de0nano.py
+++ b/targets/de0nano.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 
 from misoc.mem.sdram.module import IS42S16160
 from misoc.mem.sdram.phy import gensdrphy
diff --git a/targets/kc705.py b/targets/kc705.py
index e9cf70e4..d85e98ec 100644
--- a/targets/kc705.py
+++ b/targets/kc705.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.genlib.resetsync import AsyncResetSynchronizer
 
 from misoc.mem.sdram.module import MT8JTF12864
diff --git a/targets/minispartan6.py b/targets/minispartan6.py
index ff5e4b82..9c19122c 100644
--- a/targets/minispartan6.py
+++ b/targets/minispartan6.py
@@ -1,6 +1,6 @@
 from fractions import Fraction
 
-from migen.fhdl.std import *
+from migen import *
 from migen.genlib.resetsync import AsyncResetSynchronizer
 from migen.actorlib.fifo import SyncFIFO
 
diff --git a/targets/mlabs_video.py b/targets/mlabs_video.py
index fcd8481c..d71f6173 100644
--- a/targets/mlabs_video.py
+++ b/targets/mlabs_video.py
@@ -2,7 +2,7 @@ import os
 from fractions import Fraction
 from math import ceil
 
-from migen.fhdl.std import *
+from migen import *
 from mibuild.generic_platform import ConstraintError
 
 from misoc.mem.sdram.module import MT46V32M16
diff --git a/targets/pipistrello.py b/targets/pipistrello.py
index 668be1de..c1ca91d1 100644
--- a/targets/pipistrello.py
+++ b/targets/pipistrello.py
@@ -1,6 +1,6 @@
 from fractions import Fraction
 
-from migen.fhdl.std import *
+from migen import *
 from migen.genlib.resetsync import AsyncResetSynchronizer
 
 from misoc.mem.sdram.module import MT46H32M16
diff --git a/targets/ppro.py b/targets/ppro.py
index 1b5f43bf..c4cb89e5 100644
--- a/targets/ppro.py
+++ b/targets/ppro.py
@@ -1,6 +1,6 @@
 from fractions import Fraction
 
-from migen.fhdl.std import *
+from migen import *
 from migen.genlib.resetsync import AsyncResetSynchronizer
 
 from misoc.mem.sdram.module import MT48LC4M16
diff --git a/targets/simple.py b/targets/simple.py
index b28d5917..0c987d8e 100644
--- a/targets/simple.py
+++ b/targets/simple.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.bus import wishbone
 from migen.genlib.io import CRG
 
diff --git a/targets/versa.py b/targets/versa.py
index fd787476..237df136 100644
--- a/targets/versa.py
+++ b/targets/versa.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.bus import wishbone
 from migen.genlib.io import CRG