From: Pepijn de Vos <pepijndevos@gmail.com>
Date: Thu, 24 Oct 2019 11:39:43 +0000 (+0200)
Subject: ALU sim tweaks
X-Git-Tag: working-ls180~956^2~16
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8226f2db0b65dffb59c4420de96dccd2e0be36ed;p=yosys.git

ALU sim tweaks
---

diff --git a/techlibs/gowin/cells_sim.v b/techlibs/gowin/cells_sim.v
index 8280982d6..9dac2c2c2 100644
--- a/techlibs/gowin/cells_sim.v
+++ b/techlibs/gowin/cells_sim.v
@@ -280,16 +280,16 @@ input CIN;
 output SUM;
 output COUT;
 
-parameter ADD = 0;
-parameter SUB = 1;
-parameter ADDSUB = 2;
-parameter NE = 3;
-parameter GE = 4;
-parameter LE = 5;
-parameter CUP = 6;
-parameter CDN = 7;
-parameter CUPCDN = 8;
-parameter MULT = 9;
+localparam ADD = 0;
+localparam SUB = 1;
+localparam ADDSUB = 2;
+localparam NE = 3;
+localparam GE = 4;
+localparam LE = 5;
+localparam CUP = 6;
+localparam CDN = 7;
+localparam CUPCDN = 8;
+localparam MULT = 9;
 
 parameter ALU_MODE = 0;
 
@@ -298,7 +298,7 @@ reg S, C;
 assign SUM = S ^ CIN;
 assign COUT = S? CIN : C;
 
-always @(I0, I1, I3,CIN) begin
+always @* begin
 	case (ALU_MODE)
 		ADD: begin
 			S = I0 ^ I1;
diff --git a/tests/arch/gowin/mux.ys b/tests/arch/gowin/mux.ys
index c9c85019b..d612e4eaa 100644
--- a/tests/arch/gowin/mux.ys
+++ b/tests/arch/gowin/mux.ys
@@ -42,8 +42,8 @@ proc
 equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux16 # Constrain all select calls below inside the top module
-select -assert-count 9 t:LUT4
-select -assert-count 3 t:LUT3
+select -assert-count 10 t:LUT4
+select -assert-count 1 t:LUT3
 select -assert-count 20 t:IBUF
 select -assert-count 1 t:OBUF