From: Andrew Waterman Date: Fri, 2 Oct 2015 18:39:09 +0000 (-0700) Subject: clean up shift instruction implementation X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=82372d00398ce3712f0c7e9f243f6828041e0859;p=riscv-isa-sim.git clean up shift instruction implementation --- diff --git a/riscv/insns/slli.h b/riscv/insns/slli.h index dfe7168..26782fd 100644 --- a/riscv/insns/slli.h +++ b/riscv/insns/slli.h @@ -1,3 +1,2 @@ -if (SHAMT >= xlen) - throw trap_illegal_instruction(); +require(SHAMT < xlen); WRITE_RD(sext_xlen(RS1 << SHAMT)); diff --git a/riscv/insns/srai.h b/riscv/insns/srai.h index 69066ef..7ae1d4e 100644 --- a/riscv/insns/srai.h +++ b/riscv/insns/srai.h @@ -1,8 +1,2 @@ -if (xlen == 64) - WRITE_RD(sreg_t(RS1) >> SHAMT); -else -{ - if(SHAMT & 0x20) - throw trap_illegal_instruction(); - WRITE_RD(sext32(int32_t(RS1) >> SHAMT)); -} +require(SHAMT < xlen); +WRITE_RD(sext_xlen(sext_xlen(RS1) >> SHAMT)); diff --git a/riscv/insns/srl.h b/riscv/insns/srl.h index 0eb948b..0dabe9e 100644 --- a/riscv/insns/srl.h +++ b/riscv/insns/srl.h @@ -1,4 +1 @@ -if (xlen == 64) - WRITE_RD(RS1 >> (RS2 & 0x3F)); -else - WRITE_RD(sext32((uint32_t)RS1 >> (RS2 & 0x1F))); +WRITE_RD(sext_xlen(zext_xlen(RS1) >> (RS2 & (xlen-1)))); diff --git a/riscv/insns/srli.h b/riscv/insns/srli.h index 0cdc853..ea0b40d 100644 --- a/riscv/insns/srli.h +++ b/riscv/insns/srli.h @@ -1,8 +1,2 @@ -if (xlen == 64) - WRITE_RD(RS1 >> SHAMT); -else -{ - if(SHAMT & 0x20) - throw trap_illegal_instruction(); - WRITE_RD(sext32((uint32_t)RS1 >> SHAMT)); -} +require(SHAMT < xlen); +WRITE_RD(sext_xlen(zext_xlen(RS1) >> SHAMT));