From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Sun, 17 Feb 2019 06:22:29 +0000 (-0800)
Subject: In read_xaiger, do not construct ConstEval for every LUT
X-Git-Tag: working-ls180~1237^2~310
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=82459c16c482ad9115c742d726fd1f46527a3bab;p=yosys.git

In read_xaiger, do not construct ConstEval for every LUT
---

diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index dffbd3590..8014dd303 100644
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -290,6 +290,7 @@ void AigerReader::parse_xaiger()
                 uint32_t lutNum = parse_xaiger_literal(f);
                 uint32_t lutSize = parse_xaiger_literal(f);
                 log_debug("m: dataSize=%u lutNum=%u lutSize=%u\n", dataSize, lutNum, lutSize);
+                ConstEval ce(module);
                 for (unsigned i = 0; i < lutNum; ++i) {
                     uint32_t rootNodeID = parse_xaiger_literal(f);
                     uint32_t cutLeavesM = parse_xaiger_literal(f);
@@ -305,7 +306,6 @@ void AigerReader::parse_xaiger()
                         input_sig.append(wire);
                     }
                     RTLIL::Const lut_mask(RTLIL::State::Sx, 1 << input_sig.size());
-                    ConstEval ce(module);
                     for (int j = 0; j < (1 << cutLeavesM); ++j) {
                         ce.push();
                         ce.set(input_sig, RTLIL::Const{j, static_cast<int>(cutLeavesM)});