From: lkcl <lkcl@web>
Date: Wed, 8 Jun 2022 16:26:58 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~1910^2~1
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=824e91d39c93859b8c0e445977b5e7cedabda69b;p=libreriscv.git

---

diff --git a/openpower/sv/compliancy_levels.mdwn b/openpower/sv/compliancy_levels.mdwn
index 7ae59c950..11d54bf78 100644
--- a/openpower/sv/compliancy_levels.mdwn
+++ b/openpower/sv/compliancy_levels.mdwn
@@ -27,11 +27,13 @@ Summary of Compliancy Levels, each Level includes all lower levels:
   in both Horizontal-First and Vertical-First Mode as well as Predication
   (Single and Twin) for the GPRs r3, r10 and r30.  CR-Field-based
   Predicates, if used, may still raise illegal instruction trap.
-* **DSP/AV**: 128 registers, all SV Branch instructions,
-  crweird instructions, element-width
+* **DSP/AV**: 128 registers,
+   element-width
   overrides, and all Modes (Saturation, Fail-First, Predicate-Result,
   Mapreduce/Iteration)
-* **3D/Advanced/Supercomputing**: Matrix, DCT/FFT and Indexing
+* **3D/Advanced/Supercomputing**:  all SV Branch instructions;
+  crweird instructions;
+  Matrix, DCT/FFT and Indexing
   REMAP capability
 
 These requirements within each Level constitute the minimum mandatory
@@ -79,19 +81,19 @@ will Compliance with the Ultra-Embedded Level be achieved.
 
 This level is more suitable for Hardware implementations where performance and power saving begins to matter.  A second instruction, `svstep`, used
 by Vertical-First Mode, is required, as is hardware-level looping in
-Horizontal-First Mode. Illegal Instruction trap may not be called to
+Horizontal-First Mode. Illegal Instruction trap may not be used to
 emulate `svstep`.
 
 At the bare minimum, Twin and Single Predication must be supported for
 at least the GPRs r3, r10 and r30.  CR Field Predication may also be
 supported in hardware but only by also increasing the number of CR Fields
-to 128.
+to the required total 128.
 
 Another important aspect is that when Rc=1 is set, CR Field Vector co-results
 are produced. Should these exceed CR7 (CR8-CR127) and the number of CR Fields
 has not been increased to 128 then an Illegal Instruction Trap must be
 raised.  In practical terms, to avoid this scenario, MAXVL should not
-exceed 8 for Arithmetic or Logical operations when Rc=1.
+exceed 8 for Arithmetic or Logical operations, when Rc=1.
 
 Zeroing on source and destination for Predicates
 must also be supported (sz, dz) however
@@ -104,3 +106,10 @@ brings Hardware-level support for Predication to the entire Scalar Power
 ISA, completely without
 modifying the Scalar Power ISA.  The cost is that instructions are Prefixed
 to 64-bit.
+
+# DSP / Audio / Video Level
+
+This level is best suited to high-performance power-efficient but
+specialist Compute workloads.  128 GPRs, FPRs and CR Fields are all
+required, as is element-width overrides to allow data processing
+down to the 8-bit level.