From: Bas Nieuwenhuizen Date: Sat, 14 Jul 2018 12:28:21 +0000 (+0200) Subject: radv: Select correct entries for binning. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=82664af6cf12b1ab7436bdcb3792315c433322d7;p=mesa.git radv: Select correct entries for binning. Overshot it by one every time. CC: Reviewed-by: Samuel Pitoiset --- diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index 4c794d9515d..27e13a2251c 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -2468,7 +2468,7 @@ radv_compute_bin_size(struct radv_pipeline *pipeline, const VkGraphicsPipelineCr } const struct radv_bin_size_entry *color_entry = color_size_table[log_num_rb_per_se][log_num_se]; - while(color_entry->bpp <= color_bytes_per_pixel) + while(color_entry[1].bpp <= color_bytes_per_pixel) ++color_entry; extent = color_entry->extent; @@ -2482,7 +2482,7 @@ radv_compute_bin_size(struct radv_pipeline *pipeline, const VkGraphicsPipelineCr unsigned ds_bytes_per_pixel = 4 * (depth_coeff + stencil_coeff) * total_samples; const struct radv_bin_size_entry *ds_entry = ds_size_table[log_num_rb_per_se][log_num_se]; - while(ds_entry->bpp <= ds_bytes_per_pixel) + while(ds_entry[1].bpp <= ds_bytes_per_pixel) ++ds_entry; extent.width = MIN2(extent.width, ds_entry->extent.width);