From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 28 Feb 2022 18:10:57 +0000 (+0000)
Subject: use a slightly different yosys initialisation sequence for memory
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=826e4eef6a15bcfa659de75a5203ef31afe1dae1;p=ls2.git

use a slightly different yosys initialisation sequence for memory
---

diff --git a/simsoc.ys b/simsoc.ys
index be21ccb..4bf1530 100644
--- a/simsoc.ys
+++ b/simsoc.ys
@@ -14,8 +14,6 @@ read_verilog  ../uart16550/rtl/verilog/uart_wb.v
 read_verilog  ./external_core_top.v
 
 delete w:$verilog_initial_trigger
-proc
-memory
 proc_prune
 proc_clean
 proc_rmdead
@@ -25,13 +23,15 @@ proc_dlatch
 proc_dff
 proc_mux
 proc_rmdead
+proc_memwr
 proc_clean
+opt_expr -keepdc
+memory_collect
 pmuxtree
 #opt_mem
 #opt_mem_priority
 #opt_mem_feedback
 #opt_clean
-#memory_collect
 extract_fa
 clean
 opt