From: Richard Henderson Date: Thu, 11 Mar 1999 14:02:42 +0000 (-0800) Subject: * alpha.md (ev5_e0): Conflict loads and stores. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=827e80cc8b2870fe81e6c7857ce5d8eb78edc59e;p=gcc.git * alpha.md (ev5_e0): Conflict loads and stores. From-SVN: r25705 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 21a9c221a83..f9e698a4cd6 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -3,6 +3,8 @@ Thu Mar 11 14:00:58 1999 Richard Henderson * alpha.h (HARD_REGNO_MODE_OK): Disallow QI/HImode in fp regs. (MODES_TIEABLE_P): Update. + * alpha.md (ev5_e0): Conflict loads and stores. + Thu Mar 11 13:55:52 1999 Richard Henderson * machmode.h (smallest_mode_for_size): Prototype. diff --git a/gcc/config/alpha/alpha.md b/gcc/config/alpha/alpha.md index 82c108958c2..55bdc11c551 100644 --- a/gcc/config/alpha/alpha.md +++ b/gcc/config/alpha/alpha.md @@ -155,13 +155,18 @@ ; Memory takes at least 2 clocks. Return one from here and fix up with ; user-defined latencies in adjust_cost. -; ??? How to: "An instruction of class LD cannot be issued in the _second_ -; cycle after an instruction of class ST is issued." (define_function_unit "ev5_ebox" 2 0 (and (eq_attr "cpu" "ev5") (eq_attr "type" "ild,fld,ldsym")) 1 1) +; Loads can dual issue with one another, but loads and stores do not mix. +(define_function_unit "ev5_e0" 1 0 + (and (eq_attr "cpu" "ev5") + (eq_attr "type" "ild,fld,ldsym")) + 1 1 + [(eq_attr "type" "ist,fst")]) + ; Stores, shifts, multiplies can only issue to E0 (define_function_unit "ev5_e0" 1 0 (and (eq_attr "cpu" "ev5")