From: lkcl <lkcl@web>
Date: Tue, 20 Oct 2020 13:48:41 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~2009
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=828a1e0d9615db09212388549115ae2a68912eeb;p=libreriscv.git

---

diff --git a/conferences.mdwn b/conferences.mdwn
index b12d3530a..ac569be57 100644
--- a/conferences.mdwn
+++ b/conferences.mdwn
@@ -48,7 +48,22 @@
   - heavily depending on python OO (not possible with VHDL or Verilog)
   - leap-frogging ahead by not reinventing the wheel
 
-## What is being developed? Roadmap
+## Why is it different from other SoCs?
+
+* LibreSOC is a hybrid CPU-VPU-GPU architecture.
+  - OpenPOWER ISA *itself* is extended to include 3D and Video instructions
+  - (SIN, ATAN2, YUV2RGB, Texture Interpolation)
+  - Only after approval of OpenPOWER Foundation!
+  - Massively simplifies driver development and application debugging
+* Vectorisation is "Simple-V" (VSX not being implemented)
+  - VSX is SIMD and is considered harmful
+  - https://www.sigarch.org/simd-instructions-considered-harmful/
+* Developed in python HDL called "nmigen"
+  - OO programming techniques can be deployed
+  - Impossible to do in VHDL or Verilog
+  - yosys converts nmigen to verilog for standard tools.
+
+## What is being developed? (Roadmap)
 
 * First simple core achieved in simulation Sep 2020
   - FPGA (ECP5) target followed shortly