From: Tobias Platen Date: Fri, 21 Aug 2020 16:41:54 +0000 (+0200) Subject: connect TestCachedMemoryPortInterface to LDSTSplitter X-Git-Tag: semi_working_ecp5~277 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=829a994e274bdd4e105cf7cfd6fc465e9980b545;p=soc.git connect TestCachedMemoryPortInterface to LDSTSplitter --- diff --git a/src/soc/experiment/test/test_l0_cache_buffer2.py b/src/soc/experiment/test/test_l0_cache_buffer2.py index 35473078..ba2a8170 100644 --- a/src/soc/experiment/test/test_l0_cache_buffer2.py +++ b/src/soc/experiment/test/test_l0_cache_buffer2.py @@ -25,22 +25,22 @@ class TestCachedMemoryPortInterface(PortInterfaceBase): super().__init__(regwid, addrwid) self.ldst = LDSTSplitter(32, 48, 4) - # TODO implement these - def set_wr_addr(self, m, addr, mask): - lsbaddr, msbaddr = self.splitaddr(addr) - #m.d.comb += self.ldst... ### .eq(msbaddr) + m.d.comb += self.ldst.addr_i.eq(addr) + #lsbaddr, msbaddr = self.splitaddr(addr) def set_rd_addr(self, m, addr, mask): - lsbaddr, msbaddr = self.splitaddr(addr) + m.d.comb += self.ldst.addr_i.eq(addr) + #lsbaddr, msbaddr = self.splitaddr(addr) #m.d.comb += self..eq(msbaddr) def set_wr_data(self, m, data, wen): - #m.d.comb += self.mem.wrport.data.eq(data) # write st to mem - #m.d.comb += self.mem.wrport.en.eq(wen) # enable writes - return Const(1, 1) #document return value + m.d.comb += self.ldst.st_data_i.eq(data) # write st to mem + m.d.comb += self.ldst.is_st_i.eq(wen) # enable writes + return Const(1, 1) #fixme -- write may be longer than one cycle def get_rd_data(self, m): + # this path is still untested return self.ldst.ld_data_o.data, Const(1, 1) def elaborate(self, platform):