From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 29 Sep 2018 11:06:10 +0000 (+0100)
Subject: also arrange for id_regs.py to identify compressed instruction usage
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=82b5ca824534661602d43764152516b9a5f8526b;p=riscv-isa-sim.git

also arrange for id_regs.py to identify compressed instruction usage
---

diff --git a/id_regs.py b/id_regs.py
index b40e5ce..6b8a678 100644
--- a/id_regs.py
+++ b/id_regs.py
@@ -39,13 +39,22 @@ def list_insns():
         res.append((os.path.join(insns_dir, fname), insn))
     return res
 
-intpatterns = ['WRITE_RD', 'RS1', 'RS2', 'RS3']
+cintpatterns = [ 'WRITE_RVC_RS1S', 'WRITE_RVC_RS2S',
+                 'RVC_RS1', 'RVC_RS2', 'RVC_RS1S', 'RVC_RS2S', ]
+cfloatpatterns = [ 'WRITE_RVC_FRS2S', 'RVC_FRS2 ', 'RVC_FRS2S ']
+intpatterns   = ['WRITE_RD' , 'RS1', 'RS2', 'RS3']
 floatpatterns = ['WRITE_FRD', 'FRS1', 'FRS2', 'FRS3']
 patterns = intpatterns + floatpatterns
+patterns += cintpatterns
+patterns += cfloatpatterns
+
+allfloats = floatpatterns + cfloatpatterns
+floatmask = (1<<len(allfloats)-1)
+allints = intpatterns + cintpatterns[2:]
 
 def find_registers(fname):
     res = []
-    isintfloat = 0x0 + 0xf << 4
+    isintfloat = 0x0 + floatmask << len(allints)
     with open(fname) as f:
         f = f.read()
         for pattern in patterns:
@@ -56,15 +65,27 @@ def find_registers(fname):
                 # botch-job/hack: RS1 also matches against FRS1 (etc.)
                 # check letter before match: if "F", skip it.
                 continue
+            if pattern.startswith('R') and x != 0 and f[x-1] == '_':
+                # RS1 also matches against RVC_RS1 (etc.)
+                # check letter before match: if "_", skip it.
+                continue
+            if pattern.startswith('FR') and x != 0 and f[x-1] == '_':
+                # RS1 also matches against RVC_FRS1 (etc.)
+                # check letter before match: if "_", skip it.
+                continue
+            if 'RVC_' in pattern and f[x+len(pattern)] == 'S':
+                # RVC_RS2S also matches against RVC_RS2 (etc.)
+                # check letter at end of match: if "S", skip it.
+                continue
             p = pattern
             if p.startswith('WRITE_'):
                 p = p[6:]
-            if pattern in intpatterns:
-                idx = intpatterns.index(pattern)
+            if pattern in allints:
+                idx = allints.index(pattern)
                 isintfloat += 1 << idx
-            if pattern in floatpatterns:
-                idx = floatpatterns.index(pattern)
-                isintfloat &= ~(1 << (idx+4))
+            if pattern in allfloats:
+                idx = allfloats.index(pattern)
+                isintfloat &= ~(1 << (idx+len(allints)))
             res.append('#define USING_REG_%s' % p)
     if not res:
         return '#define USING_NOREGS\n' \
diff --git a/riscv/sv_decode.h b/riscv/sv_decode.h
index 727cf77..e80fab0 100644
--- a/riscv/sv_decode.h
+++ b/riscv/sv_decode.h
@@ -11,6 +11,11 @@
 #define REG_RS1 0x2
 #define REG_RS2 0x4
 #define REG_RS3 0x8
+#define REG_RVC_RS1 0x10
+#define REG_RVC_RS2 0x20
+#define REG_RVC_RS1S 0x40
+#define REG_RVC_RS2S 0x80
+
 
 class sv_insn_t: public insn_t
 {