From: Giacomo Travaglini Date: Tue, 12 May 2020 08:42:15 +0000 (+0100) Subject: misc: Add Arm contributions to gem5-20 RELEASE-NOTES.md X-Git-Tag: v20.0.0.0~36 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=82c24005dd71701d071e881f3e90321a4b1a0c92;p=gem5.git misc: Add Arm contributions to gem5-20 RELEASE-NOTES.md * Arm architectural extensions * Arm TFA support * DRAM changes Change-Id: I434c501ee8413c8cd64af25c2c18eabf45e3ee77 Signed-off-by: Giacomo Travaglini Reviewed-by: Nikos Nikoleris Reviewed-by: Wendy Elsasser Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28908 Reviewed-by: Jason Lowe-Power Maintainer: Jason Lowe-Power Tested-by: kokoro --- diff --git a/RELEASE-NOTES.md b/RELEASE-NOTES.md index 6f80906b2..0e52e5dba 100644 --- a/RELEASE-NOTES.md +++ b/RELEASE-NOTES.md @@ -9,3 +9,11 @@ * Robust support for marshalling data from a function call inside the simulation to a function within gem5 using a predefined set of rules. * Workload configuration pulled out into its own object, simplifying the System object and making workload configuration more modular and flexible. * Sv39 paging has been added to the RISC-V ISA, bringing gem5 close to running Linux on RISC-V. +* Implemented ARMv8.3-CompNum, SIMD complex number extension. +* Support for Arm Trusted Firmware + u-boot with the new VExpress_GEM5_Foundation platform. +* Changes in the DRAM Controller: + 1) Added support for verifying available command bandwidth. + 2) Added support for multi-cycle commands. + 3) Added new timing parameters. + 4) Added ability to interleave bursts. + 5) Added LPDDR5 configurations.