From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 4 Jun 2019 18:54:08 +0000 (-0700)
Subject: Add space between -D and _ABC
X-Git-Tag: working-ls180~1208^2~202
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=82d41bc2f2460a06e153eac4f3968ef29ce5a63d;p=yosys.git

Add space between -D and _ABC
---

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 360418975..e9eccfc0e 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -203,9 +203,9 @@ struct SynthXilinxPass : public ScriptPass
 	{
 		if (check_label("begin")) {
 			if (vpr)
-				run("read_verilog -lib -D_ABC -D_EXPLICIT_CARRY +/xilinx/cells_sim.v");
+				run("read_verilog -lib -D _ABC -D_EXPLICIT_CARRY +/xilinx/cells_sim.v");
 			else
-				run("read_verilog -lib -D_ABC +/xilinx/cells_sim.v");
+				run("read_verilog -lib -D _ABC +/xilinx/cells_sim.v");
 
 			run("read_verilog -lib +/xilinx/cells_xtra.v");