From: lkcl <lkcl@web>
Date: Fri, 6 May 2022 17:13:49 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2363
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=82dde2967a2b6c8c30a9f41191c9a28053545d17;p=libreriscv.git

---

diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn
index 5bcde068c..95349f6cc 100644
--- a/openpower/sv/SimpleV_rationale.mdwn
+++ b/openpower/sv/SimpleV_rationale.mdwn
@@ -678,5 +678,10 @@ is entirely transparent to the developer, in fact this is a hard requirement
 because at any given moment there is the possibility that the PEs may be
 busy and it is the main CPU that has to complete the Processing Task itself.
 
-It
+It is also important to note that we are not necessarily talking about
+the Remote PEs executing the Power ISA, but if they do so it becomes
+much easier for the main CPU to take over in the event that PEs are
+currently occupied.  Plus, the twin lessons that inventing ISAs, even
+a small one, is hard (mostly in compiler writing) and how complex
+GPU Task Scheduling is, are being heard loud and clear.