From: Ilia Mirkin <imirkin@alum.mit.edu>
Date: Sat, 20 May 2017 07:11:12 +0000 (-0400)
Subject: nvc0/ir: SHLADD's middle source must be an immediate
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=82e77d4e4484b5d4f6a7b4751a17c882e6d2ad69;p=mesa.git

nvc0/ir: SHLADD's middle source must be an immediate

The instruction encodings only allow for immediates. Don't try to
replace a zero (which is dumb to have in that op in any case) with RZ.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org
---

diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
index 732e1a93b42..64d743708a6 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
@@ -642,6 +642,8 @@ NVC0LegalizePostRA::replaceZero(Instruction *i)
    for (int s = 0; i->srcExists(s); ++s) {
       if (s == 2 && i->op == OP_SUCLAMP)
          continue;
+      if (s == 1 && i->op == OP_SHLADD)
+         continue;
       ImmediateValue *imm = i->getSrc(s)->asImm();
       if (imm) {
          if (i->op == OP_SELP && s == 2) {