From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 2 Jul 2020 23:09:47 +0000 (+0100)
Subject: use Mock class (more convenient)
X-Git-Tag: div_pipeline~167
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=82eb031f84f451d587f0ac5202b3235a9ce90813;p=soc.git

use Mock class (more convenient)
---

diff --git a/src/soc/config/test/test_loadstore.py b/src/soc/config/test/test_loadstore.py
index 1676967a..8d906c70 100644
--- a/src/soc/config/test/test_loadstore.py
+++ b/src/soc/config/test/test_loadstore.py
@@ -6,10 +6,10 @@ from nmigen.back.pysim import Simulator, Settle
 from soc.config.loadstore import ConfigLoadStoreUnit
 from collections import namedtuple
 from nmigen.cli import rtlil
+from unittest.mock import Mock
+
+TestMemPspec = Mock # might as well use Mock, it does the job
 
-TestMemPspec = namedtuple('TestMemPspec', ['ldst_ifacetype',
-                             'imem_ifacetype',
-                             'addr_wid', 'mask_wid', 'reg_wid'])
 
 def write_to_addr(dut, addr, value):
     yield dut.x_addr_i.eq(addr)