From: Gabe Black <gblack@eecs.umich.edu>
Date: Mon, 13 Aug 2007 23:01:09 +0000 (-0700)
Subject: Move the "translate" member functions back into the base o3 class.
X-Git-Tag: m5_2.0_beta4~187
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=82f78ebd39943a55a94f952f22f3f5a993460e88;p=gem5.git

Move the "translate" member functions back into the base o3 class.

--HG--
extra : convert_revision : 3c480537bf38f74f0f1d72e75c70aa46ba91b759
---

diff --git a/src/cpu/o3/alpha/cpu.hh b/src/cpu/o3/alpha/cpu.hh
index 676893098..ebc4e7b23 100644
--- a/src/cpu/o3/alpha/cpu.hh
+++ b/src/cpu/o3/alpha/cpu.hh
@@ -66,45 +66,6 @@ class AlphaO3CPU : public FullO3CPU<Impl>
     /** Registers statistics. */
     void regStats();
 
-#if FULL_SYSTEM
-    /** Translates instruction requestion. */
-    Fault translateInstReq(RequestPtr &req, Thread *thread)
-    {
-        return this->itb->translate(req, thread->getTC());
-    }
-
-    /** Translates data read request. */
-    Fault translateDataReadReq(RequestPtr &req, Thread *thread)
-    {
-        return this->dtb->translate(req, thread->getTC(), false);
-    }
-
-    /** Translates data write request. */
-    Fault translateDataWriteReq(RequestPtr &req, Thread *thread)
-    {
-        return this->dtb->translate(req, thread->getTC(), true);
-    }
-
-#else
-    /** Translates instruction requestion in syscall emulation mode. */
-    Fault translateInstReq(RequestPtr &req, Thread *thread)
-    {
-        return thread->getProcessPtr()->pTable->translate(req);
-    }
-
-    /** Translates data read request in syscall emulation mode. */
-    Fault translateDataReadReq(RequestPtr &req, Thread *thread)
-    {
-        return thread->getProcessPtr()->pTable->translate(req);
-    }
-
-    /** Translates data write request in syscall emulation mode. */
-    Fault translateDataWriteReq(RequestPtr &req, Thread *thread)
-    {
-        return thread->getProcessPtr()->pTable->translate(req);
-    }
-
-#endif
     /** Reads a miscellaneous register. */
     TheISA::MiscReg readMiscRegNoEffect(int misc_reg, unsigned tid);
 
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index 84a7c8673..7d7e4e24d 100644
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -94,9 +94,9 @@ class FullO3CPU : public BaseO3CPU
   public:
     // Typedefs from the Impl here.
     typedef typename Impl::CPUPol CPUPolicy;
-    typedef typename Impl::Params Params;
     typedef typename Impl::DynInstPtr DynInstPtr;
     typedef typename Impl::O3CPU O3CPU;
+    typedef typename Impl::Params Params;
 
     typedef O3ThreadState<Impl> Thread;
 
@@ -265,6 +265,46 @@ class FullO3CPU : public BaseO3CPU
     /** Registers statistics. */
     void fullCPURegStats();
 
+#if FULL_SYSTEM
+    /** Translates instruction requestion. */
+    Fault translateInstReq(RequestPtr &req, Thread *thread)
+    {
+        return this->itb->translate(req, thread->getTC());
+    }
+
+    /** Translates data read request. */
+    Fault translateDataReadReq(RequestPtr &req, Thread *thread)
+    {
+        return this->dtb->translate(req, thread->getTC(), false);
+    }
+
+    /** Translates data write request. */
+    Fault translateDataWriteReq(RequestPtr &req, Thread *thread)
+    {
+        return this->dtb->translate(req, thread->getTC(), true);
+    }
+
+#else
+    /** Translates instruction requestion in syscall emulation mode. */
+    Fault translateInstReq(RequestPtr &req, Thread *thread)
+    {
+        return thread->getProcessPtr()->pTable->translate(req);
+    }
+
+    /** Translates data read request in syscall emulation mode. */
+    Fault translateDataReadReq(RequestPtr &req, Thread *thread)
+    {
+        return thread->getProcessPtr()->pTable->translate(req);
+    }
+
+    /** Translates data write request in syscall emulation mode. */
+    Fault translateDataWriteReq(RequestPtr &req, Thread *thread)
+    {
+        return thread->getProcessPtr()->pTable->translate(req);
+    }
+
+#endif
+
     /** Returns a specific port. */
     Port *getPort(const std::string &if_name, int idx);
 
diff --git a/src/cpu/o3/mips/cpu.hh b/src/cpu/o3/mips/cpu.hh
index 0361c1814..3724ced46 100755
--- a/src/cpu/o3/mips/cpu.hh
+++ b/src/cpu/o3/mips/cpu.hh
@@ -68,24 +68,6 @@ class MipsO3CPU : public FullO3CPU<Impl>
     /** Registers statistics. */
     void regStats();
 
-    /** Translates instruction requestion in syscall emulation mode. */
-    Fault translateInstReq(RequestPtr &req, Thread *thread)
-    {
-        return thread->getProcessPtr()->pTable->translate(req);
-    }
-
-    /** Translates data read request in syscall emulation mode. */
-    Fault translateDataReadReq(RequestPtr &req, Thread *thread)
-    {
-        return thread->getProcessPtr()->pTable->translate(req);
-    }
-
-    /** Translates data write request in syscall emulation mode. */
-    Fault translateDataWriteReq(RequestPtr &req, Thread *thread)
-    {
-        return thread->getProcessPtr()->pTable->translate(req);
-    }
-
     /** Reads a miscellaneous register. */
     TheISA::MiscReg readMiscRegNoEffect(int misc_reg, unsigned tid);
 
diff --git a/src/cpu/o3/sparc/cpu.hh b/src/cpu/o3/sparc/cpu.hh
index 7b932e429..3fd193e0f 100644
--- a/src/cpu/o3/sparc/cpu.hh
+++ b/src/cpu/o3/sparc/cpu.hh
@@ -66,45 +66,6 @@ class SparcO3CPU : public FullO3CPU<Impl>
     /** Registers statistics. */
     void regStats();
 
-#if FULL_SYSTEM
-    /** Translates instruction requestion. */
-    Fault translateInstReq(RequestPtr &req, Thread *thread)
-    {
-        return this->itb->translate(req, thread->getTC());
-    }
-
-    /** Translates data read request. */
-    Fault translateDataReadReq(RequestPtr &req, Thread *thread)
-    {
-        return this->dtb->translate(req, thread->getTC(), false);
-    }
-
-    /** Translates data write request. */
-    Fault translateDataWriteReq(RequestPtr &req, Thread *thread)
-    {
-        return this->dtb->translate(req, thread->getTC(), true);
-    }
-
-#else
-    /** Translates instruction requestion in syscall emulation mode. */
-    Fault translateInstReq(RequestPtr &req, Thread *thread)
-    {
-        return thread->getProcessPtr()->pTable->translate(req);
-    }
-
-    /** Translates data read request in syscall emulation mode. */
-    Fault translateDataReadReq(RequestPtr &req, Thread *thread)
-    {
-        return thread->getProcessPtr()->pTable->translate(req);
-    }
-
-    /** Translates data write request in syscall emulation mode. */
-    Fault translateDataWriteReq(RequestPtr &req, Thread *thread)
-    {
-        return thread->getProcessPtr()->pTable->translate(req);
-    }
-
-#endif
     /** Reads a miscellaneous register. */
     TheISA::MiscReg readMiscRegNoEffect(int misc_reg, unsigned tid);