From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 16 Aug 2020 12:16:22 +0000 (+0100)
Subject: fix LD/ST pimem issue with rising_edge detection
X-Git-Tag: semi_working_ecp5~316
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=830d7d7efd5381c0abf7c739c380a9884a3be09c;p=soc.git

fix LD/ST pimem issue with rising_edge detection
---

diff --git a/src/soc/experiment/compldst_multi.py b/src/soc/experiment/compldst_multi.py
index 5ec52268..7606ade5 100644
--- a/src/soc/experiment/compldst_multi.py
+++ b/src/soc/experiment/compldst_multi.py
@@ -362,6 +362,8 @@ class LDSTCompUnit(RegSpecAPI, Elaboratable):
         oper_r = CompLDSTOpSubset(name="oper_r")  # Dest register
         with m.If(self.issue_i):
             sync += oper_r.eq(self.oper_i)
+        with m.If(self.done_o):
+            sync += oper_r.eq(0)
 
         # and for LD
         ldd_r = Signal(self.data_wid, reset_less=True)  # Dest register
diff --git a/src/soc/experiment/pimem.py b/src/soc/experiment/pimem.py
index 279e8971..492b7c2e 100644
--- a/src/soc/experiment/pimem.py
+++ b/src/soc/experiment/pimem.py
@@ -22,6 +22,7 @@ from nmutil.iocontrol import RecordObject
 from nmigen.utils import log2_int
 
 from nmutil.latch import SRLatch, latchregister
+from nmutil.util import rising_edge
 from soc.decoder.power_decoder2 import Data
 from soc.scoreboard.addr_match import LenExpand
 
@@ -193,8 +194,8 @@ class PortInterfaceBase(Elaboratable):
         comb += busy_edge.eq(pi.busy_o & ~busy_delay)
 
         # activate mode: only on "edge"
-        comb += ld_active.s.eq(lds & busy_edge)  # activate LD mode
-        comb += st_active.s.eq(sts & busy_edge)  # activate ST mode
+        comb += ld_active.s.eq(rising_edge(m, lds))  # activate LD mode
+        comb += st_active.s.eq(rising_edge(m, sts))  # activate ST mode
 
         # LD/ST requested activates "busy" (only if not already busy)
         with m.If(self.pi.is_ld_i | self.pi.is_st_i):