From: Gabe Black <gblack@eecs.umich.edu>
Date: Thu, 6 Apr 2006 19:21:52 +0000 (-0400)
Subject: Fixed for full system.
X-Git-Tag: m5_2.0_beta1~138
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=832311a17094501a6883100ac9dba8c781211782;p=gem5.git

Fixed for full system.

--HG--
extra : convert_revision : 28c9cd55d887c9de7156c8cf76b7b91117f749d5
---

diff --git a/arch/alpha/regfile.hh b/arch/alpha/regfile.hh
index 2a3312584..af01b7829 100644
--- a/arch/alpha/regfile.hh
+++ b/arch/alpha/regfile.hh
@@ -162,9 +162,9 @@ namespace AlphaISA
 #if FULL_SYSTEM
         int intrflag;			// interrupt flag
         inline int instAsid()
-        { return miscRegs.getInstAsid(); }
+        { return miscRegFile.getInstAsid(); }
         inline int dataAsid()
-        { return miscRegs.getDataAsid(); }
+        { return miscRegFile.getDataAsid(); }
 #endif // FULL_SYSTEM
 
         void clear()
diff --git a/cpu/cpu_exec_context.hh b/cpu/cpu_exec_context.hh
index feaf29d12..c74feec68 100644
--- a/cpu/cpu_exec_context.hh
+++ b/cpu/cpu_exec_context.hh
@@ -497,7 +497,7 @@ class CPUExecContext
     int readIntrFlag() { return regs.intrflag; }
     void setIntrFlag(int val) { regs.intrflag = val; }
     Fault hwrei();
-    bool inPalMode() { return AlphaISA::PcPAL(regs.pc); }
+    bool inPalMode() { return AlphaISA::PcPAL(regs.readPC()); }
     bool simPalCheck(int palFunc);
 #endif