From: Sudakshina Das <sudi.das@arm.com>
Date: Thu, 14 Dec 2017 10:35:38 +0000 (+0000)
Subject: [PATCH PR81228][AARCH64]Fix ICE by adding LTGT in vec_cmp<mode><v_int_equiv>
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8332c5ee8c5f3bf91eb97666793e9589f2578a05;p=gcc.git

[PATCH PR81228][AARCH64]Fix ICE by adding LTGT in vec_cmp<mode><v_int_equiv>

This patch is a follow up to the existing discussions on
https://gcc.gnu.org/ml/gcc-patches/2017-07/msg01904.html
Bin had earlier submitted this patch to fix the ICE that
occurs because of the missing LTGT in aarch64-simd.md.
That discussion opened up a new bug report PR81647 for
an inconsistent behavior.

As discussed earlier on the gcc-patches discussion and on
the bug report, PR81647 was occurring because of how UNEQ
was handled in aarch64-simd.md rather than LTGT.
Since __builtin_islessgreater is guaranteed to not give an
FP exception but LTGT might, __builtin_islessgreater gets
converted to ~UNEQ very early on in fold_builtin_unordered_cmp.
Thus I will post a separate patch for correcting how UNEQ and
other unordered comparisons are handled in aarch64-simd.md.

This patch is only adding the missing LTGT to plug the ICE.

Testing done: Checked for regressions on bootstrapped
aarch64-none-linux-gnu and added a new compile time test case
that gives out LTGT to make sure it doesn't ICE

*** gcc/ChangeLog ***

2017-12-14  Sudakshina Das  <sudi.das@arm.com>
	    Bin Cheng  <bin.cheng@arm.com>

	PR target/81228
	* config/aarch64/aarch64.c (aarch64_select_cc_mode): Move LTGT
	to CCFPEmode.
	* config/aarch64/aarch64-simd.md (vec_cmp<mode><v_int_equiv>): Add
	LTGT.

*** gcc/testsuite/ChangeLog ***

2017-12-14  Sudakshina Das  <sudi.das@arm.com>

	PR target/81228
	* gcc.dg/pr81228.c: New.

Co-Authored-By: Bin Cheng <bin.cheng@arm.com>

From-SVN: r255625
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 5e18fb9aa89..e33b45f34ea 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,12 @@
+2017-12-14  Sudakshina Das  <sudi.das@arm.com>
+	    Bin Cheng  <bin.cheng@arm.com>
+
+	PR target/81228
+	* config/aarch64/aarch64.c (aarch64_select_cc_mode): Move LTGT
+	to CCFPEmode.
+	* config/aarch64/aarch64-simd.md (vec_cmp<mode><v_int_equiv>): Add
+	LTGT.
+
 2017-12-14  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 
 	* config/aarch64/aarch64-cores.def (cortex-a55, cortex-a75,
diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index ae71af83343..f90f74fe7fd 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -2759,6 +2759,7 @@
     case UNEQ:
     case ORDERED:
     case UNORDERED:
+    case LTGT:
       break;
     default:
       gcc_unreachable ();
@@ -2813,6 +2814,15 @@
       emit_insn (gen_one_cmpl<v_int_equiv>2 (operands[0], operands[0]));
       break;
 
+    case LTGT:
+      /* LTGT is not guranteed to not generate a FP exception.  So let's
+	 go the faster way : ((a > b) || (b > a)).  */
+      emit_insn (gen_aarch64_cmgt<mode> (operands[0],
+					 operands[2], operands[3]));
+      emit_insn (gen_aarch64_cmgt<mode> (tmp, operands[3], operands[2]));
+      emit_insn (gen_ior<v_int_equiv>3 (operands[0], operands[0], tmp));
+      break;
+
     case UNORDERED:
       /* Operands are ORDERED iff (a > b || b >= a), so we can compute
 	 UNORDERED as !ORDERED.  */
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index fc157fa6219..b9c17fc5ccc 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -4962,13 +4962,13 @@ aarch64_select_cc_mode (RTX_CODE code, rtx x, rtx y)
 	case UNGT:
 	case UNGE:
 	case UNEQ:
-	case LTGT:
 	  return CCFPmode;
 
 	case LT:
 	case LE:
 	case GT:
 	case GE:
+	case LTGT:
 	  return CCFPEmode;
 
 	default:
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 802146b4ee2..51f7b33e840 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2017-12-14  Sudakshina Das  <sudi.das@arm.com>
+
+	PR target/81228
+	* gcc.dg/pr81228.c: New.
+
 2017-12-14  Jakub Jelinek  <jakub@redhat.com>
 
 	PR c++/79650
diff --git a/gcc/testsuite/gcc.dg/pr81228.c b/gcc/testsuite/gcc.dg/pr81228.c
new file mode 100644
index 00000000000..f7eecc510ad
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/pr81228.c
@@ -0,0 +1,21 @@
+/* PR target/81228.  */
+/* { dg-do compile } */
+/* { dg-options "-O3 -fdump-tree-ssa" } */
+
+void *a;
+
+void b ()
+{
+  char c;
+  long d;
+  char *e = a;
+  for (; d; d++)
+  {
+    double f, g;
+    c = g < f || g > f;
+    e[d] = c;
+  }
+}
+
+/* Let's make sure we do have a LTGT.  */
+/* { dg-final { scan-tree-dump "<>" "ssa" } } */