From: lkcl <lkcl@web>
Date: Thu, 26 May 2022 09:42:04 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2082
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=83441cb0528ccc33e462c38fa05b9c8a5f34b17a;p=libreriscv.git

---

diff --git a/openpower/sv/int_fp_mv.mdwn b/openpower/sv/int_fp_mv.mdwn
index 4d21a5752..55cb67bec 100644
--- a/openpower/sv/int_fp_mv.mdwn
+++ b/openpower/sv/int_fp_mv.mdwn
@@ -368,6 +368,16 @@ This instruction is present in ARM assembler as FJCVTZS
 |--------|------|--------|-------|-------|----|------|
 |  Major | RT   | //Mode | FRA   | XO    | Rc |X-Form|
 
+**Rc=1 and OE=1**
+
+All of these insructions have an Rc=1 mode which sets CR0
+in the normal way for any instructions producing a GPR result.
+Additionally, when OE=1, if the numerical value of the FP number
+is not 100% accurately preserved (due to truncation or saturation
+and including when the FP number was NaN) then this is considered
+to be an integer Overflow condition, and CR0.SO, XER.SO and XER.OV
+are all set as normal for any GPR instructions that overflow.
+
 **Instructions**
 
 * `fcvttgw RT, FRA, Mode`