From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Tue, 22 Jan 2019 11:50:05 +0000 (+0100)
Subject: soc/cores/clock: add USIDELAYCTRL
X-Git-Tag: 24jan2021_ls180~1403
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8344a6a4ef87a065e9c9213040a72be6439ab857;p=litex.git

soc/cores/clock: add USIDELAYCTRL
---

diff --git a/litex/soc/cores/clock.py b/litex/soc/cores/clock.py
index 44858447..8e2a24ba 100644
--- a/litex/soc/cores/clock.py
+++ b/litex/soc/cores/clock.py
@@ -385,6 +385,23 @@ class USMMCM(USClocking):
             self.params["o_CLKOUT{}".format(n)] = clk
         self.specials += Instance("MMCME2_ADV", **self.params)
 
+
+class USIDELAYCTRL(Module):
+    def __init__(self, cd):
+        reset_counter = Signal(6, reset=63)
+        ic_reset = Signal(reset=1)
+        sync = getattr(self.sync, cd.name)
+        sync += \
+            If(reset_counter != 0,
+                reset_counter.eq(reset_counter - 1)
+            ).Else(
+                ic_reset.eq(0)
+            )
+        self.specials += Instance("IDELAYCTRL",
+            p_SIM_DEVICE="ULTRASCALE",
+            i_REFCLK=cd.clk,
+            i_RST=ic_reset)
+
 # Lattice / ECP5
 
 # TODO: