From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 7 Jun 2020 21:11:48 +0000 (+0100)
Subject: update comments
X-Git-Tag: div_pipeline~482
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8346d298529e5f0128da91ebd45c14485ade2a30;p=soc.git

update comments
---

diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py
index 83f07be0..3f94019e 100644
--- a/src/soc/decoder/isa/caller.py
+++ b/src/soc/decoder/isa/caller.py
@@ -235,8 +235,8 @@ class ISACaller:
 
     def TRAP(self, trap_addr=0x700):
         print ("TRAP: TODO")
-        # store PC in SRR0, set PC to 0x700
-        # store MSR in SRR1, set MSR to um errr something
+        # store CIA(+4?) in SRR0, set NIA to 0x700
+        # store MSR in SRR1, set MSR to um errr something, have to check spec
 
     def memassign(self, ea, sz, val):
         self.mem.memassign(ea, sz, val)