From: lkcl Date: Wed, 12 Apr 2023 14:00:39 +0000 (+0100) Subject: (no commit message) X-Git-Tag: opf_rfc_ls010_v1~53 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=834b0e8450499da9db632e2315162cfc5034e609;p=libreriscv.git --- diff --git a/openpower/sv/cr_ops.mdwn b/openpower/sv/cr_ops.mdwn index 1da2cc3a1..426bc530e 100644 --- a/openpower/sv/cr_ops.mdwn +++ b/openpower/sv/cr_ops.mdwn @@ -229,6 +229,36 @@ The "weird" operations have a non-standard behaviour, being able to treat *individual bits* of a GPR effectively as elements. They are expected to be Micro-coded by most Hardware implementations. +## Effectively-separate Vector and Scalar Condition Register file + +As mentioned in the introduction on [[sv/svp64]] some prohibitions +are made on instructions involving Condition Registers that allow +implementors to actually consider the Scalar CR (fields CR0-CR7) +as a completely separate register file from the Vector CRs +(fields CR8-CR127). + +The complications arise for existing Hardware implementations +due to Power ISA not having had "Conditional Execution" added. +Adding entirely new pipelines and a new Vector CR Register file +is a much easier proposition to consider. + +The prohibitions utilise the CR Field numbers implicitly to +split out Vectorised CR operations to be considered completely +separare and distinct from Scalar CR operations *even though +they both use the same binary encoding*. This does in turn +mean that at the Decode Phase it becomes necessary to examine +not only the operation (`sv.crand`, `sv.cmp`) but also +the CR Field numbers as well as whether, in the EXTRA2/3 Mode +bits, the operands are Vectorised. + +A future version of Power ISA, where SVP64Single is proposed, +would in fact introduce "Conditional Execution", including +for VSX. At which point this prohibition becomes moot as +Predication would be required to be added into the existing +Scalar (and PackedSIMD VSX) side of existing Power ISA +implementations. + + -------- [[!tag standards]]