From: lkcl <lkcl@web>
Date: Mon, 8 Jun 2020 21:49:58 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~2503
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=834ca1530901395fc69f44d3a51ed1972ce8fc75;p=libreriscv.git

---

diff --git a/Documentation/SOC/index.mdwn b/Documentation/SOC/index.mdwn
index e2eafc086..24ccdc85a 100644
--- a/Documentation/SOC/index.mdwn
+++ b/Documentation/SOC/index.mdwn
@@ -53,3 +53,9 @@ This should give you a feel for how we work with enums and PowerOP.
     verilog =  verilog.convert(top, name='top', strip_internal_attrs=True, ports= top.op_add.ports())
     f.write(verilog)
     print(f"Verilog Written to: {verilog_file}")
+
+The [actual POWER9 Decoder](https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/decoder/power_decoder2.py;hb=HEAD)
+uses this principle, in conjunction with reading the information shown in the table above, from CSV files as opposed to hardcoding them in python source.
+
+This demonstrates one of the design aspects taken in this project: to *combine* the power of python's full capabilities in order to create advanced dynamically generated HDL, rather than (as done with MyHDL) limit python code to a subset of its full capabilities.
+