From: Marek Olšák Date: Tue, 1 May 2018 02:48:00 +0000 (-0400) Subject: radeonsi: remove r600_fmask_info X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=835095973df84e3970582c6a3d4a9729990ddda2;p=mesa.git radeonsi: remove r600_fmask_info radeon_surf contains almost everything. Reviewed-by: Nicolai Hähnle --- diff --git a/src/gallium/drivers/radeonsi/si_blit.c b/src/gallium/drivers/radeonsi/si_blit.c index 1cbd26f46e0..6f4cd1f9044 100644 --- a/src/gallium/drivers/radeonsi/si_blit.c +++ b/src/gallium/drivers/radeonsi/si_blit.c @@ -470,7 +470,7 @@ static void si_blit_decompress_color(struct si_context *sctx, if (!vi_dcc_enabled(rtex, i)) level_mask &= ~(1 << i); } - } else if (rtex->fmask.size) { + } else if (rtex->surface.fmask_size) { custom_blend = sctx->custom_blend_fmask_decompress; } else { custom_blend = sctx->custom_blend_eliminate_fastclear; @@ -528,7 +528,7 @@ si_decompress_color_texture(struct si_context *sctx, struct r600_texture *tex, unsigned first_level, unsigned last_level) { /* CMASK or DCC can be discarded and we can still end up here. */ - if (!tex->cmask.size && !tex->fmask.size && !tex->dcc_offset) + if (!tex->cmask.size && !tex->surface.fmask_size && !tex->dcc_offset) return; si_blit_decompress_color(sctx, tex, first_level, last_level, 0, @@ -849,7 +849,7 @@ static void si_decompress_subresource(struct pipe_context *ctx, si_decompress_depth(sctx, rtex, planes, level, level, first_layer, last_layer); - } else if (rtex->fmask.size || rtex->cmask.size || rtex->dcc_offset) { + } else if (rtex->surface.fmask_size || rtex->cmask.size || rtex->dcc_offset) { /* If we've rendered into the framebuffer and it's a blitting * source, make sure the decompression pass is invoked * by dirtying the framebuffer. diff --git a/src/gallium/drivers/radeonsi/si_clear.c b/src/gallium/drivers/radeonsi/si_clear.c index 0de51488f59..8ecd47fea9b 100644 --- a/src/gallium/drivers/radeonsi/si_clear.c +++ b/src/gallium/drivers/radeonsi/si_clear.c @@ -577,7 +577,7 @@ static void si_clear(struct pipe_context *ctx, unsigned buffers, continue; tex = (struct r600_texture *)fb->cbufs[i]->texture; - if (tex->fmask.size == 0) + if (tex->surface.fmask_size == 0) tex->dirty_level_mask &= ~(1 << fb->cbufs[i]->u.tex.level); } } diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c index 9f2433a5b72..1d14c9df1e1 100644 --- a/src/gallium/drivers/radeonsi/si_descriptors.c +++ b/src/gallium/drivers/radeonsi/si_descriptors.c @@ -467,7 +467,7 @@ static void si_set_sampler_view_desc(struct si_context *sctx, desc); } - if (!is_buffer && rtex->fmask.size) { + if (!is_buffer && rtex->surface.fmask_size) { memcpy(desc + 8, sview->fmask_state, 8*4); } else { /* Disable FMASK and bind sampler state in [12:15]. */ @@ -482,7 +482,7 @@ static void si_set_sampler_view_desc(struct si_context *sctx, static bool color_needs_decompression(struct r600_texture *rtex) { - return rtex->fmask.size || + return rtex->surface.fmask_size || (rtex->dirty_level_mask && (rtex->cmask.size || rtex->dcc_offset)); } @@ -714,13 +714,13 @@ static void si_set_shader_image_desc(struct si_context *ctx, * so we don't wanna trigger it. */ if (tex->is_depth || - (!fmask_desc && tex->fmask.size != 0)) { + (!fmask_desc && tex->surface.fmask_size != 0)) { assert(!"Z/S and MSAA image stores are not supported"); access &= ~PIPE_IMAGE_ACCESS_WRITE; } assert(!tex->is_depth); - assert(fmask_desc || tex->fmask.size == 0); + assert(fmask_desc || tex->surface.fmask_size == 0); if (uses_dcc && !skip_decompress && (view->access & PIPE_IMAGE_ACCESS_WRITE || @@ -980,7 +980,7 @@ static void si_bind_sampler_states(struct pipe_context *ctx, sview->base.texture->target != PIPE_BUFFER) tex = (struct r600_texture *)sview->base.texture; - if (tex && tex->fmask.size) + if (tex && tex->surface.fmask_size) continue; si_set_sampler_state_desc(sstates[i], sview, tex, diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h index 27efc5099f0..b5caf944759 100644 --- a/src/gallium/drivers/radeonsi/si_pipe.h +++ b/src/gallium/drivers/radeonsi/si_pipe.h @@ -230,17 +230,6 @@ struct r600_transfer { unsigned offset; }; -struct r600_fmask_info { - uint64_t offset; - uint64_t size; - unsigned alignment; - unsigned pitch_in_pixels; - unsigned bank_height; - unsigned slice_tile_max; - unsigned tile_mode_index; - unsigned tile_swizzle; -}; - struct r600_cmask_info { uint64_t offset; uint64_t size; @@ -257,7 +246,7 @@ struct r600_texture { struct r600_texture *flushed_depth_texture; /* Colorbuffer compression and fast clear. */ - struct r600_fmask_info fmask; + uint64_t fmask_offset; struct r600_cmask_info cmask; struct r600_resource *cmask_buffer; uint64_t dcc_offset; /* 0 = disabled */ @@ -1230,10 +1219,6 @@ bool si_prepare_for_dma_blit(struct si_context *sctx, struct r600_texture *rsrc, unsigned src_level, const struct pipe_box *src_box); -void si_texture_get_fmask_info(struct si_screen *sscreen, - struct r600_texture *rtex, - unsigned nr_samples, - struct r600_fmask_info *out); void si_texture_get_cmask_info(struct si_screen *sscreen, struct r600_texture *rtex, struct r600_cmask_info *out); diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index 0c4e6d08855..f7878ed2367 100644 --- a/src/gallium/drivers/radeonsi/si_state.c +++ b/src/gallium/drivers/radeonsi/si_state.c @@ -2414,9 +2414,9 @@ static void si_initialize_color_surface(struct si_context *sctx, color_attrib |= S_028C74_NUM_SAMPLES(log_samples) | S_028C74_NUM_FRAGMENTS(log_samples); - if (rtex->fmask.size) { + if (rtex->surface.fmask_size) { color_info |= S_028C70_COMPRESSION(1); - unsigned fmask_bankh = util_logbase2(rtex->fmask.bank_height); + unsigned fmask_bankh = util_logbase2(rtex->surface.u.legacy.fmask.bankh); if (sctx->chip_class == SI) { /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */ @@ -2449,7 +2449,7 @@ static void si_initialize_color_surface(struct si_context *sctx, } /* This must be set for fast clear to work without FMASK. */ - if (!rtex->fmask.size && sctx->chip_class == SI) { + if (!rtex->surface.fmask_size && sctx->chip_class == SI) { unsigned bankh = util_logbase2(rtex->surface.u.legacy.bankh); color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh); } @@ -2664,7 +2664,7 @@ void si_update_fb_dirtiness_after_rendering(struct si_context *sctx) struct pipe_surface *surf = sctx->framebuffer.state.cbufs[i]; struct r600_texture *rtex = (struct r600_texture*)surf->texture; - if (rtex->fmask.size) + if (rtex->surface.fmask_size) rtex->dirty_level_mask |= 1 << surf->u.tex.level; if (rtex->dcc_gather_statistics) rtex->separate_dcc_dirty = true; @@ -2836,7 +2836,7 @@ static void si_set_framebuffer_state(struct pipe_context *ctx, if (surf->color_is_int10) sctx->framebuffer.color_is_int10 |= 1 << i; - if (rtex->fmask.size) + if (rtex->surface.fmask_size) sctx->framebuffer.compressed_cb_mask |= 1 << i; else sctx->framebuffer.uncompressed_cb_mask |= 1 << i; @@ -2987,9 +2987,9 @@ static void si_emit_framebuffer_state(struct si_context *sctx) if (cb->base.u.tex.level > 0) cb_color_info &= C_028C70_FAST_CLEAR; - if (tex->fmask.size) { - cb_color_fmask = (tex->buffer.gpu_address + tex->fmask.offset) >> 8; - cb_color_fmask |= tex->fmask.tile_swizzle; + if (tex->surface.fmask_size) { + cb_color_fmask = (tex->buffer.gpu_address + tex->fmask_offset) >> 8; + cb_color_fmask |= tex->surface.fmask_tile_swizzle; } /* Set up DCC. */ @@ -3018,7 +3018,7 @@ static void si_emit_framebuffer_state(struct si_context *sctx) /* Set mutable surface parameters. */ cb_color_base += tex->surface.u.gfx9.surf_offset >> 8; cb_color_base |= tex->surface.tile_swizzle; - if (!tex->fmask.size) + if (!tex->surface.fmask_size) cb_color_fmask = cb_color_base; if (cb->base.u.tex.level > 0) cb_color_cmask = cb_color_base; @@ -3058,7 +3058,7 @@ static void si_emit_framebuffer_state(struct si_context *sctx) if (level_info->mode == RADEON_SURF_MODE_2D) cb_color_base |= tex->surface.tile_swizzle; - if (!tex->fmask.size) + if (!tex->surface.fmask_size) cb_color_fmask = cb_color_base; if (cb->base.u.tex.level > 0) cb_color_cmask = cb_color_base; @@ -3074,11 +3074,11 @@ static void si_emit_framebuffer_state(struct si_context *sctx) cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max); cb_color_slice = S_028C68_TILE_MAX(slice_tile_max); - if (tex->fmask.size) { + if (tex->surface.fmask_size) { if (sctx->chip_class >= CIK) - cb_color_pitch |= S_028C64_FMASK_TILE_MAX(tex->fmask.pitch_in_pixels / 8 - 1); - cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tex->fmask.tile_mode_index); - cb_color_fmask_slice = S_028C88_TILE_MAX(tex->fmask.slice_tile_max); + cb_color_pitch |= S_028C64_FMASK_TILE_MAX(tex->surface.u.legacy.fmask.pitch_in_pixels / 8 - 1); + cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tex->surface.u.legacy.fmask.tiling_index); + cb_color_fmask_slice = S_028C88_TILE_MAX(tex->surface.u.legacy.fmask.slice_tile_max); } else { /* This must be set for fast clear to work without FMASK. */ if (sctx->chip_class >= CIK) @@ -3736,10 +3736,10 @@ si_make_texture_descriptor(struct si_screen *screen, } /* Initialize the sampler view for FMASK. */ - if (tex->fmask.size) { + if (tex->surface.fmask_size) { uint32_t data_format, num_format; - va = tex->buffer.gpu_address + tex->fmask.offset; + va = tex->buffer.gpu_address + tex->fmask_offset; if (screen->info.chip_class >= GFX9) { data_format = V_008F14_IMG_DATA_FORMAT_FMASK; @@ -3773,7 +3773,7 @@ si_make_texture_descriptor(struct si_screen *screen, num_format = V_008F14_IMG_NUM_FORMAT_UINT; } - fmask_state[0] = (va >> 8) | tex->fmask.tile_swizzle; + fmask_state[0] = (va >> 8) | tex->surface.fmask_tile_swizzle; fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) | S_008F14_DATA_FORMAT_GFX6(data_format) | S_008F14_NUM_FORMAT_GFX6(num_format); @@ -3796,9 +3796,9 @@ si_make_texture_descriptor(struct si_screen *screen, fmask_state[5] |= S_008F24_META_PIPE_ALIGNED(tex->surface.u.gfx9.cmask.pipe_aligned) | S_008F24_META_RB_ALIGNED(tex->surface.u.gfx9.cmask.rb_aligned); } else { - fmask_state[3] |= S_008F1C_TILING_INDEX(tex->fmask.tile_mode_index); + fmask_state[3] |= S_008F1C_TILING_INDEX(tex->surface.u.legacy.fmask.tiling_index); fmask_state[4] |= S_008F20_DEPTH(depth - 1) | - S_008F20_PITCH_GFX6(tex->fmask.pitch_in_pixels - 1); + S_008F20_PITCH_GFX6(tex->surface.u.legacy.fmask.pitch_in_pixels - 1); fmask_state[5] |= S_008F24_LAST_ARRAY(last_layer); } } diff --git a/src/gallium/drivers/radeonsi/si_texture.c b/src/gallium/drivers/radeonsi/si_texture.c index 3fd34af338d..81a70153f32 100644 --- a/src/gallium/drivers/radeonsi/si_texture.c +++ b/src/gallium/drivers/radeonsi/si_texture.c @@ -564,7 +564,7 @@ static void si_reallocate_texture_inplace(struct si_context *sctx, rtex->can_sample_z = new_tex->can_sample_z; rtex->can_sample_s = new_tex->can_sample_s; rtex->surface = new_tex->surface; - rtex->fmask = new_tex->fmask; + rtex->fmask_offset = new_tex->fmask_offset; rtex->cmask = new_tex->cmask; rtex->cb_color_info = new_tex->cb_color_info; rtex->last_msaa_resolve_target_micro_mode = new_tex->last_msaa_resolve_target_micro_mode; @@ -578,7 +578,7 @@ static void si_reallocate_texture_inplace(struct si_context *sctx, if (new_bind_flag == PIPE_BIND_LINEAR) { assert(!rtex->htile_offset); assert(!rtex->cmask.size); - assert(!rtex->fmask.size); + assert(!rtex->surface.fmask_size); assert(!rtex->dcc_offset); assert(!rtex->is_depth); } @@ -612,7 +612,7 @@ static void si_query_opaque_metadata(struct si_screen *sscreen, return; assert(rtex->dcc_separate_buffer == NULL); - assert(rtex->fmask.size == 0); + assert(rtex->surface.fmask_size == 0); /* Metadata image format format version 1: * [0] = 1 (metadata format identifier) @@ -845,38 +845,6 @@ static void si_texture_destroy(struct pipe_screen *screen, static const struct u_resource_vtbl si_texture_vtbl; -/* The number of samples can be specified independently of the texture. */ -void si_texture_get_fmask_info(struct si_screen *sscreen, - struct r600_texture *rtex, - unsigned nr_samples, - struct r600_fmask_info *out) -{ - if (sscreen->info.chip_class >= GFX9) { - out->alignment = rtex->surface.fmask_alignment; - out->size = rtex->surface.fmask_size; - out->tile_swizzle = rtex->surface.fmask_tile_swizzle; - return; - } - - out->slice_tile_max = rtex->surface.u.legacy.fmask.slice_tile_max; - out->tile_mode_index = rtex->surface.u.legacy.fmask.tiling_index; - out->pitch_in_pixels = rtex->surface.u.legacy.fmask.pitch_in_pixels; - out->bank_height = rtex->surface.u.legacy.fmask.bankh; - out->tile_swizzle = rtex->surface.fmask_tile_swizzle; - out->alignment = rtex->surface.fmask_alignment; - out->size = rtex->surface.fmask_size; -} - -static void si_texture_allocate_fmask(struct si_screen *sscreen, - struct r600_texture *rtex) -{ - si_texture_get_fmask_info(sscreen, rtex, - rtex->buffer.b.b.nr_samples, &rtex->fmask); - - rtex->fmask.offset = align64(rtex->size, rtex->fmask.alignment); - rtex->size = rtex->fmask.offset + rtex->fmask.size; -} - void si_texture_get_cmask_info(struct si_screen *sscreen, struct r600_texture *rtex, struct r600_cmask_info *out) @@ -1049,10 +1017,10 @@ void si_print_texture_info(struct si_screen *sscreen, rtex->surface.u.gfx9.surf.epitch, rtex->surface.u.gfx9.surf_pitch); - if (rtex->fmask.size) { + if (rtex->surface.fmask_size) { u_log_printf(log, " FMASK: offset=%"PRIu64", size=%"PRIu64", " "alignment=%u, swmode=%u, epitch=%u\n", - rtex->fmask.offset, + rtex->fmask_offset, rtex->surface.fmask_size, rtex->surface.fmask_alignment, rtex->surface.u.gfx9.fmask.swizzle_mode, @@ -1104,12 +1072,14 @@ void si_print_texture_info(struct si_screen *sscreen, rtex->surface.u.legacy.tile_split, rtex->surface.u.legacy.pipe_config, (rtex->surface.flags & RADEON_SURF_SCANOUT) != 0); - if (rtex->fmask.size) + if (rtex->surface.fmask_size) u_log_printf(log, " FMask: offset=%"PRIu64", size=%"PRIu64", alignment=%u, pitch_in_pixels=%u, " "bankh=%u, slice_tile_max=%u, tile_mode_index=%u\n", - rtex->fmask.offset, rtex->fmask.size, rtex->fmask.alignment, - rtex->fmask.pitch_in_pixels, rtex->fmask.bank_height, - rtex->fmask.slice_tile_max, rtex->fmask.tile_mode_index); + rtex->fmask_offset, rtex->surface.fmask_size, rtex->surface.fmask_alignment, + rtex->surface.u.legacy.fmask.pitch_in_pixels, + rtex->surface.u.legacy.fmask.bankh, + rtex->surface.u.legacy.fmask.slice_tile_max, + rtex->surface.u.legacy.fmask.tiling_index); if (rtex->cmask.size) u_log_printf(log, " CMask: offset=%"PRIu64", size=%"PRIu64", alignment=%u, " @@ -1248,11 +1218,15 @@ si_texture_create_object(struct pipe_screen *screen, if (base->nr_samples > 1 && !buf && !(sscreen->debug_flags & DBG(NO_FMASK))) { - si_texture_allocate_fmask(sscreen, rtex); + /* Allocate FMASK. */ + rtex->fmask_offset = align64(rtex->size, + rtex->surface.fmask_alignment); + rtex->size = rtex->fmask_offset + rtex->surface.fmask_size; + si_texture_allocate_cmask(sscreen, rtex); rtex->cmask_buffer = &rtex->buffer; - if (!rtex->fmask.size || !rtex->cmask.size) { + if (!rtex->surface.fmask_size || !rtex->cmask.size) { FREE(rtex); return NULL; }