From: lkcl <lkcl@web>
Date: Mon, 22 Feb 2021 04:18:54 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~136
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=835af896e45fe18a5dc4d1f36cc9c5a8059d836d;p=libreriscv.git

---

diff --git a/openpower/sv/implementation.mdwn b/openpower/sv/implementation.mdwn
index c2018946d..39e023c97 100644
--- a/openpower/sv/implementation.mdwn
+++ b/openpower/sv/implementation.mdwn
@@ -151,6 +151,10 @@ TODO.  INTs, FPs, CRs, these all increase to 128.  Welcome To Vector ISAs.
 
 At the same time the `Rc=1` CR offsets normslly CR0 and CR1 for fixed and FP scalar may also be adjusted.
 
+## Exception Handling
+
+When excceptions occur, and SRR0 and SRR1 are saved and restored, SVSTATE in SVSRR0 must now likewise be saved and restored.
+
 ## Single Predication
 
 TODO