From: lkcl <lkcl@web>
Date: Sun, 26 Jun 2022 12:26:42 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~1518
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8369b2b081676f6f7c5969d4d345f531ed723cc5;p=libreriscv.git

---

diff --git a/openpower/sv/svp64/appendix.mdwn b/openpower/sv/svp64/appendix.mdwn
index 75a08fa8c..4fcacdb09 100644
--- a/openpower/sv/svp64/appendix.mdwn
+++ b/openpower/sv/svp64/appendix.mdwn
@@ -464,7 +464,9 @@ operation.  Identification
 of such is trivial to do for `setb` and `cmp`: the source register type is
 a completely different register file from the destination.
 Likewise Scalar reduction when the destination is a Vector
-is as if the Reduction Mode was not requested.*
+is as if the Reduction Mode was not requested. However it would clearly
+be unacceptable to perform such optimisations on cache-inhibited LD/ST,
+so some considerable care needs to be taken.*
 
 Typical applications include simple operations such as `ADD r3, r10.v,
 r3` where, clearly, r3 is being used to accumulate the addition of all