From: Clifford Wolf <clifford@clifford.at>
Date: Wed, 19 Jun 2019 15:25:39 +0000 (+0200)
Subject: Merge pull request #1109 from YosysHQ/clifford/fix1106
X-Git-Tag: yosys-0.9~67
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=8395f837c33a1f08ed67995ef8274219b0af27c8;p=yosys.git

Merge pull request #1109 from YosysHQ/clifford/fix1106

Add "read_verilog -pwires" feature
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8395f837c33a1f08ed67995ef8274219b0af27c8