From: Sudakshina Das <sudi.das@arm.com>
Date: Wed, 21 Mar 2018 17:14:48 +0000 (+0000)
Subject: [ARM] Fix test pr82989.c for big endian and mthumb
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=839c95d00b92ca2d9e8e3cfac023be93bab2b5c6;p=gcc.git

[ARM] Fix test pr82989.c for big endian and mthumb

The test pr82989.c which was added in one of previous commits is failing for
mthumb and big-endian configurations. The aim of this test was to check that
NEON instructions are not being used for simple shift operations. The scanning
of lsl and lsr instructions and checking its counts were just too restrictive
for different configurations. So I have now simplified the test to only check
for the absence of NEON instructions.

*** gcc/testsuite/ChangeLog ***

2018-03-21  Sudakshina Das  <sudi.das@arm.com>

	PR target/82989
	* gcc.target/arm/pr82989.c: Change dg scan-assembly directives.

From-SVN: r258723
---

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 4422bdf5308..b302528eff6 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2018-03-21  Sudakshina Das  <sudi.das@arm.com>
+
+	PR target/82989
+	* gcc.target/arm/pr82989.c: Change dg scan-assembly directives.
+
 2018-03-21  Nathan Sidwell  <nathan@acm.org>
 
 	PR c++/84804
diff --git a/gcc/testsuite/gcc.target/arm/pr82989.c b/gcc/testsuite/gcc.target/arm/pr82989.c
index 6f74dba44dd..8519c3fdc82 100644
--- a/gcc/testsuite/gcc.target/arm/pr82989.c
+++ b/gcc/testsuite/gcc.target/arm/pr82989.c
@@ -13,26 +13,21 @@ void f_shr_imm (uint64_t *a)
 {
   *a += *a >> 32;
 }
-/* { dg-final { scan-assembler-not "vshr*" } } */
 
 void f_shr_reg (uint64_t *a, uint64_t b)
 {
   *a += *a >> b;
 }
-/* { dg-final { scan-assembler-not "vshl*" } } */
-/* Only 2 times for f_shr_reg. f_shr_imm should not have any.  */
-/* { dg-final { scan-assembler-times {lsr\tr[0-9]+, r[0-9]+, r[0-9]} 2 } } */
 
 void f_shl_imm (uint64_t *a)
 {
   *a += *a << 32;
 }
-/* { dg-final { scan-assembler-not "vshl*" } } */
 
 void f_shl_reg (uint64_t *a, uint64_t b)
 {
   *a += *a << b;
 }
 /* { dg-final { scan-assembler-not "vshl*" } } */
-/* Only 2 times for f_shl_reg. f_shl_imm should not have any.  */
-/* { dg-final { scan-assembler-times {lsl\tr[0-9]+, r[0-9]+, r[0-9]} 2 } } */
+/* { dg-final { scan-assembler-not "vshr*" } } */
+/* { dg-final { scan-assembler-not "vmov*" } } */