From: Luke Kenneth Casson Leighton Date: Tue, 29 Mar 2022 19:43:58 +0000 (+0100) Subject: add err wishbone feature to Tercel X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=83a828d37759cfedf97687532a8b4858562f2d9e;p=ls2.git add err wishbone feature to Tercel --- diff --git a/src/ls2.py b/src/ls2.py index 3152245..92c990b 100644 --- a/src/ls2.py +++ b/src/ls2.py @@ -411,7 +411,7 @@ class DDR3SoC(SoC, Elaboratable): # The main SPI Flash (SPI 1) should be set to at # least 28 bits (256MB) to allow the use of large 4BA devices. self.spi0 = Tercel(data_width=32, spi_region_addr_width=24, - features={'stall'}, + features={'stall', 'err'}, clk_freq=clk_freq, pins=spi_0_pins, lattice_ecp5_usrmclk=spi0_is_lattice_ecp5_clk)