From: Luke Kenneth Casson Leighton Date: Mon, 3 Apr 2023 09:57:15 +0000 (+0100) Subject: clarify UnVectorised RESERVED X-Git-Tag: opf_rfc_ls012_v1~168 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=83b1ae3bd720bbaa1310c58343af0655ecd99435;p=libreriscv.git clarify UnVectorised RESERVED --- diff --git a/openpower/sv/svp64.mdwn b/openpower/sv/svp64.mdwn index 728e09c9a..57b54d7f3 100644 --- a/openpower/sv/svp64.mdwn +++ b/openpower/sv/svp64.mdwn @@ -39,7 +39,7 @@ Table of contents [[!toc]] -# Introduction +## Introduction Simple-V is a type of Vectorisation best described as a "Prefix Loop Subsystem" similar to the 5 decades-old Zilog Z80 `LDIR` instruction and @@ -463,8 +463,8 @@ they may equally be allocated entirely differently. different Defined Words be allocated within any `EXT{z}` prefixed or unprefixed space for a given value of `z`. Even if UnVectoriseable an instruction Defined Word space must have the exact same Instruction -and exact same Instruction Encoding in all spaces (including -being RESERVED if UnVectoriseable) or not be allocated at all. +and exact same Instruction Encoding in all spaces being RESERVED - Illegal +Instruction Trap - if UnVectoriseable) or not be allocated at all. This is required as an inviolate hard rule governing Primary Opcode 9 that may not be revoked under any circumstances. A useful way to think of this is that the Prefix Encoding is, like the 8086 REP instruction, @@ -1053,7 +1053,8 @@ Now at its own page: [[svp64/appendix]] -------- +[[!tag standards]] + \newpage{} -[[!tag standards]]