From: Miodrag Milanovic <mmicko@gmail.com>
Date: Fri, 22 Apr 2022 10:04:05 +0000 (+0200)
Subject: latches are always set to zero
X-Git-Tag: yosys-0.17~23^2~4
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=83cad82b295255d59e2162d599bbd4485b688c6a;p=yosys.git

latches are always set to zero
---

diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc
index 73e03067b..f480168bd 100644
--- a/passes/sat/sim.cc
+++ b/passes/sat/sim.cc
@@ -1815,12 +1815,7 @@ struct AIWWriter : public OutputWriter
 				for (int i = 0;; i++)
 				{
 					if (aiw_latches.count(i)) {
-						SigBit bit = aiw_latches.at(i).first;
-						auto v = current[mapping[bit.wire]].bits.at(bit.offset);
-						if (v == State::S1)
-							aiwfile << (aiw_latches.at(i).second ? '0' : '1');
-						else
-							aiwfile << (aiw_latches.at(i).second ? '1' : '0');
+						aiwfile << '0';
 						continue;
 					}
 					aiwfile << '\n';