From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 5 Dec 2021 12:35:20 +0000 (+0000)
Subject: more signal sizes in icache.py
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=83cec6b1a6d62b4d5ecf54591178c333612f2974;p=soc.git

more signal sizes in icache.py
---

diff --git a/src/soc/experiment/icache.py b/src/soc/experiment/icache.py
index fac91b27..a4a6fac5 100644
--- a/src/soc/experiment/icache.py
+++ b/src/soc/experiment/icache.py
@@ -349,7 +349,7 @@ class ICache(Elaboratable):
             d_out    = Signal(ROW_SIZE_BITS, name="d_out_%d" % i)
             wr_sel   = Signal(ROW_SIZE)
 
-            way = CacheRam(ROW_BITS, ROW_SIZE_BITS, True)
+            way = CacheRam(ROW_BITS, ROW_SIZE_BITS, True, ram_num=i)
             setattr(m.submodules, "cacheram_%d" % i, way)
 
             comb += way.rd_en.eq(do_read)
@@ -607,7 +607,7 @@ class ICache(Elaboratable):
                     )
 
             # Keep track of our index and way for subsequent stores
-            st_row = Signal(BRAM_ROWS)
+            st_row = Signal(ROW_BITS)
             comb += st_row.eq(get_row(req_laddr))
             sync += r.store_index.eq(req_index)
             sync += r.store_row.eq(st_row)