From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 13 Dec 2019 18:26:37 +0000 (-0800)
Subject: opt_merge to discard \init of '$' cells with 'Q' port when merging
X-Git-Tag: working-ls180~818^2~3
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=83d36394f86510abf944ada407d4a1f4d7eefcd0;p=yosys.git

opt_merge to discard \init of '$' cells with 'Q' port when merging
---

diff --git a/passes/opt/opt_merge.cc b/passes/opt/opt_merge.cc
index aaea6159e..643cf0215 100644
--- a/passes/opt/opt_merge.cc
+++ b/passes/opt/opt_merge.cc
@@ -323,6 +323,17 @@ struct OptMergeWorker
 									log_signal(it.second), log_signal(other_sig));
 							module->connect(RTLIL::SigSig(it.second, other_sig));
 							assign_map.add(it.second, other_sig);
+
+							if (cell->type.begins_with("$") && it.first == ID(Q)) {
+								for (auto c : it.second.chunks()) {
+									auto jt = c.wire->attributes.find(ID(init));
+									if (jt == c.wire->attributes.end())
+										continue;
+									for (int i = c.offset; i < c.offset + c.width; i++)
+										jt->second[i] = State::Sx;
+								}
+								dff_init_map.add(it.second, Const(State::Sx, GetSize(it.second)));
+							}
 						}
 					}
 					log_debug("    Removing %s cell `%s' from module `%s'.\n", cell->type.c_str(), cell->name.c_str(), module->name.c_str());